3

4887D–AUTO–12/06

ATA6621

2.

Pin Configuration

Figure 2-1.

Pinning QFN20

67

8

10

9

20

19

18

MLP 5 mm

× 5 mm

0.65 mm pitch

20 lead

ATA6621

16

11

12

13

14

15

TXD

NRES

WD_OSC

TM

MODE

GND

WAKE

NTRIG

PTRIG

EN

5

4

3

2

1

17

Table 2-1.

Pin Description

Pin

Symbol

Function

1

EN

Enables the device into Normal Mode

2

PTRIG

High-level watchdog trigger input from microcontroller; if not needed, leave open or connect to GND

3

NTRIG

Low-level watchdog trigger input from microcontroller; if not needed, leave open or connect to VCC

4

WAKE

High-voltage input for local wake-up request; if not needed, connect to VS

5

GND

System ground

6

NC

Not connected

7

LIN

LIN bus line input/output

8

NC

Not connected

9

RXD

Receive data output

10

NC

Not connected

11

TXD

Transmit data input; active low output (strong pull down) after a local wake-up request

12

NRES

Output undervoltage and watchdog reset

13

WD_OSC

External resistor for adjustable watchdog timing

14

TM

For factory testing only (tie to ground)

15

MODE

For debug mode, high watchdog off, low watchdog on

16

GND

Additional ground

17

TEMP

Chip temperature output pin; if not needed connect to GND

18

PVCC

5V regulator sense input pin

19

VCC

5V regulator output/driver pin

20

VS

Battery supply

Backside

Heat slug is connected to GND (pin 5)