DP83816 datasheet(71/106 Pages) NSC

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4.0 Register Set (Continued)

4.3.9 PHY Status Register

This register provides a single location within the register set for quick access to commonly accessed information.

ACK2

Acknowledge2: Default: 0

1 = Will comply with message

0 = Cannot comply with message

Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply

with the message received.

TOG_TX

Toggle: Default: 0, RO

1 = Value of toggle bit in previously transmitted Link Code Word was 0

0 = Value of toggle bit in previously transmitted Link Code Word was 1

Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization with the Link

Partner during Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the

previously exchanged Link Code Word.

10:0

CODE

Code Field: Default: <000 0000 0001>

This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this

802.3u. Otherwise, the code shall be interpreted as an "Un-formatted Page”, and the interpretation is

application specific.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

Tag: PHYSTS

Size: 16 bits

Hard Reset: 0000h

Offset: 00C0h

Access: Read Only

Bit

Bit Name

Description

15:14

Reserved

Reserved: Write ignored, read as 0.

Receive Error

Latch

Receive Error Latch:

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT (address 0xD4)

0 = No receive error event has occurred

Polarity

Status

Polarity Status:

This bit is a duplication of bit 4 in the TBTSCR register. This bit will be cleared upon a read of the TBTSCR

1 = Inverted Polarity detected

0 = Correct Polarity detected

False Carrier

Sense Latch

False Carrier Sense Latch: Default: 0, RO/LH

This bit will be cleared upon a read of the FCSCR register.

1 = False Carrier event has occurred since last read of FCSCR (address 0xD0)

0 = No False Carrier event has occurred

Signal Detect Signal Detect: Default: 0, RO/LL

100BASE-TX unconditional Signal Detect from PMD.

De-scrambler

Lock

De-scrambler Lock: Default: 0, RO/LL

100BASE-TX De-scrambler Lock from PMD.

Page

Received

Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a

read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 0x98, bit 1)

0 = Link Code Word Page has not been received

MII Interrupt

MII Interrupt Pending: Default: 0, RO/LH

1 = Indicates that an internal interrupt is pending, cleared by the current read

0 = No interrupt pending

Bit

Bit Name

Description

DP83816 Datasheet(PDF) 71 Page - National Semiconductor (TI)

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