DP83816 datasheet(13/106 Pages) NSC

13 / 106 page

3.0 Functional Description (Continued)

www.national.com

Little Endian (CFG:BEM=0): The byte orientation for

receive and transmit data in system memory is as follows:

Big Endian (CFG:BEM=1): The byte orientation for

receive and transmit data in system memory is as follows:

3.1.1.2 PCI Bus Interrupt Control

PCI bus interrupts for the DP83816 are asynchronously

performed by asserting pin INTAN. This pin is an open

drain output. The source of the interrupt can be determined

by reading the Interrupt Status Register (ISR). One or more

bits in the ISR will be set, denoting all currently pending

interrupts. Caution: Reading of the ISR clears ALL bits.

Masking of specified interrupts can be accomplished by

using the Interrupt Mask Register (IMR).

3.1.1.3 Timer

The Latency Timer described in CFGLAT:LAT defines the

minimum number of bus clocks that the device will hold the

bus. Once the device gains control of the bus and issues

FRAMEN, the Latency Timer will begin counting down. If

GNTN is de-asserted before the DP83816 has finished

with the bus, the device will maintain ownership of the bus

until the timer reaches zero (or has finished the bus

transfer). The timer is an 8-bit counter.

3.1.2 Tx MAC

This block implements the transmit portion of 802.3 Media

Access Control. The Tx MAC retrieves packet data from

the Tx Buffer Manager and sends it out through the

transmit portion. Additionally, the Tx MAC provides MIB

control information for transmit packets.

3.1.3 Rx MAC

This block implements the receive portion of 802.3 Media

Access Control. The Rx MAC retrieves packet data from

the receive portion and sends it to the Rx Buffer Manager.

Additionally, the Rx MAC provides MIB control information

and packet address data for the Rx Filter.

3.2 Buffer Management

The buffer management scheme used on the DP83816

allows quick, simple and efficient use of the frame buffer

memory. Frames are saved in similar formats for both

transmit and receive. The buffer management scheme also

uses separate buffers and descriptors for packet

information. This allows effective transfers of data from the

receive buffer to the transmit buffer by simply transferring

the descriptor from the receive queue to the transmit

queue.

The format of the descriptors allows the packets to be

saved in a number of configurations. A packet can be

stored in memory with a single descriptor per single packet,

or multiple descriptors per single packet. This flexibility

allows the user to configure the DP83816 to maximize

efficiency. Architecture of the specific system’s buffer

memory, as well as the nature of network traffic, will

determine the most suitable configuration of packet

descriptors

and

fragments.

Refer

the

Buffer

Management Section (Section 5.0) for more information.

3.2.1 Tx Buffer Manager

This block DMAs packet data from PCI memory space and

places it in the 2 KB transmit FIFO, and pulls data from the

FIFO to send to the Tx MAC. Multiple packets (4) may be

present in the FIFO, allowing packets to be transmitted with

minimum interframe gap. The way in which the FIFO is

emptied and filled is controlled by the FIFO threshold

values in the TXCFG register: FLTH (Tx Fill Threshold) and

DRTH (Tx Drain Threshold). These values determine how

full or empty the FIFO must be before the device requests

the bus. Additionally, once the DP83816 requests the bus,

it will attempt to empty or fill the FIFO as allowed by the

MXDMA setting in the TXCFG register.

3.2.2 Rx Buffer Manager

This block retrieves packet data from the Rx MAC and

places it in the 2 KB receive data FIFO, and pulls data from

the FIFO for DMA to PCI memory space. The Rx Buffer

Manager maintains a status FIFO, allowing up to 4 packets

to reside in the FIFO at once. Similar to the transmit FIFO,

the receive FIFO is controlled by the FIFO threshold value

in the RXCFG register: DRTH (Rx Drain Threshold). This

value determines the number of long words written into the

FIFO from the MAC unit before a DMA request for system

memory access occurs. Once the DP83816 gets the bus, it

will continue to transfer the long words from the FIFO until

the data in the FIFO is less than one long word, or has

reached the end of the packet, or the max DMA burst size

is reached (RXCFG:MXDMA).

3.2.3 Packet Recognition

The Receive packet filter and recognition logic allows

software to control which packets are accepted based on

destination address and packet type. Address recognition

logic includes support for broadcast, multicast hash, and

unicast addresses. The packet recognition logic includes

support for WOL, Pause, and programmable pattern

recognition.

The standard 802.3 Ethernet packet consists of the

following fields: Preamble (PA), Start of Frame Delimiter

(SFD), Destination Address (DA), Source Address (SA),

Length (LEN), Data and Frame Check Sequence (FCS). All

fields are fixed length except for the data field. During

reception, the PA, SFD and FCS are stripped. During

transmission, the DP83816 generates and appends the

PA, SFD and FCS.

Byte 0

Byte 1

Byte 2

Byte 3

LSB

C/BE[0]

C/BE[1]

C/BE[2]

C/BE[3]

MSB

Byte 3

Byte 2

Byte 1

Byte 0

MSB

C/BE[0]

C/BE[1]

C/BE[2]

C/BE[3]

LSB

DP83816 Datasheet(PDF) 13 Page - National Semiconductor (TI)

DP83816 Datasheet(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL