DP83816 datasheet(89/106 Pages) NSC

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6.0 Power Management and Wake-On-LAN (Continued)

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6.5.2 Wake Events

If the device detects a wake event while in WOL mode, it

will assert the PMEN pin low to signal the system that a

wake event has occurred. The system should then bring

the device out of WOL mode as described below.

6.5.3 Exiting WOL Mode

The following steps are required to bring the device out of

WOL mode (with or without an accompanying wake event):

If the Power Management state is D3cold, the system

will assert PCI reset, restore PCI bus power, and

restart the PCI clock. This will also return the Power

State to D0. The PCI configuration registers (i.e. base

addresses, bus master enable, etc.) must be reinitial-

ized.

Write a 0 to Power State bits [0:1] in the PMCSR (in

case the WOL Power State was not D3hot or D3cold)

and PME Enable. These can be done in one opera-

tion, or Power State can be written first. Turning off

PME Enable will cause the device to de-assert the

PMEN pin, if it was asserted.

If the WOL Power State was D3hot or D3cold, reinitial-

ize the PCI configuration registers (i.e. base

addresses, bus master enable, etc.). An ACPI-com-

patible operating system should handle this step. Note

that operational registers will not be accessible until

this step is completed.

If a wake event occurred, read the WCSR to deter-

mine what the event was.

Write a 1 to PME Status. This will clear any wake

event in the device. An ACPI-compatible operating

system will perform this write to the PMCSR; a driver

can perform this write using the Clockrun Control/Sta-

tus Register (CCSR).

If the wake event was a PHY interrupt from an internal

PHY, clear the event in the PHY registers. Refer to the

MISR in Section 4.3.11.

Clear all bits in WCSR.

Disable the receiver by writing a 1 to the Receiver Dis-

able bit in the Command Register (CR:RXD).

Reconfigure RFCR as appropriate for normal opera-

tion.

10. Write a valid receive descriptor pointer to the Receive

Descriptor Pointer Register (RXDP)

11. Enable the receiver by writing a 1 to the Receiver

Enable bit in the Command Register (CR:RXE). If the

wake event was a packet, this will now be emptied

from the receive FIFO via DMA.

6.6 Sleep Mode

Sleep Mode is a system-level function that allows a device

to be placed in a lower power mode than WOL mode. In

sleep mode, the device will not be able to detect wake

events or signal the system that it needs service.

6.6.1 Entering Sleep Mode

The following steps are required to enter Sleep Mode:

Disable the receiver by writing a 1 to the Receiver Dis-

able bit in the Command Register (CR:RXD).

Write 0 to the Receive Descriptor Pointer Register

(RXDP)

Force the receiver to reread the descriptor pointer by

writing a 1 to the Receiver Enable bit in the Command

Do not configure any wake events in WCSR.

Write a 0 to PME Enable, and set the desired Power

State in PMCSR. These can be done in one operation.

An ACPI-compatible operating system should handle

this step.

If the Power Management state is D3cold, the system

will assert PCI reset, stop the PCI clock, and remove

power from the PCI bus.

6.6.2 Exiting Sleep Mode

The following steps are required to bring the DP83816 out

of Sleep Mode:

If the Power Management state is D3cold, the system

will assert PCI reset, restore PCI bus power, and

restart the PCI clock. This will also return the Power

State to D0. The PCI configuration registers (i.e. base

addresses, bus master enable, etc.) must be reinitial-

ized.

Write a 0 to Power State bits [0:1] in the PMCSR (in

case the sleep Power State was not D3hot or D3cold).

If the sleep Power State was D3hot or D3cold, reinitial-

izeaddresses, bus master enable, etc.). An ACPI-com-

patible operating system should handle this step. Note

that operational registers will not be accessible until

this step is completed.

Disable the receiver by writing a 1 to the Receiver Dis-

able bit in the Command Register (CR:RXD).

Write a valid receive descriptor pointer to the Receive

Descriptor Pointer Register (RXDP)

Enable the receiver by writing a 1 to the Receiver

Enable bit in the Command Register (CR:RXE).

6.7 Pin Configuration for Power Management

Refer to Table 6-2 for proper pin connection for power

management configuration:

Note: *Refer to Demo Board schematics for additional information.

Table 6-2 PM Pin Configuration

Pin Name Pin No. Power Mgt No Power Mgt

PMEN

*PME#

3.3V

3VAUX

122

*3.3Vaux

GND

DP83816 Datasheet(PDF) 89 Page - National Semiconductor (TI)

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