M2040 datasheet(2/12 Pages) ICST

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M2040 Datasheet Rev 1.0

2 of 12

Revised 28Jan2005

I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0

Integrated

Circuit

Systems, Inc.

M2040

FREQUENCY TRANSLATION PLL WITH AUTOSWITCH

Prod uct Data Sh eet

PIN DESCRIPTIONS

Number

Name

I/O

Configuration

Description

1, 2, 3, 10, 14, 26

GND

Ground

Power supply ground connections.

OP_IN

nOP_IN

Input

External loop filter connections. See Figure 5,

External Loop Filter, on pg. 7.

nOP_OUT

OP_OUT

Output

nVC

Input

11, 19, 33

VCC

Power

Power supply connection, connect to +3.3V.

FOUT1

nFOUT1

Output

No internal terminator

Clock output pair 1. Differential LVPECL.

FOUT0

nFOUT0

Output

No internal terminator

Clock output pair 0. Differential LVPECL.

INIT

Input

Internal pull-UP resistor1

Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 8.

Power-on Initialization; LVCMOS/LVTTL:

Logic 1 allows device to enter narrow mode if

selected (in addition must have 8 LOL=0 counts)

Logic 0 forced device into wide bandwidth mode.

P_SEL

Internal pull-down1

Post-PLL , P divider selection. LVCMOS/LVTTL.

See Table 5, P Divider Selector Values

and Frequencies, on pg. 3.

nDIF_REF1

Input

Biased to Vcc/2 2

Note 2: Biased to Vcc/2, with 50k

Ω to Vcc and 50kΩto ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 8.

Reference

clock input

pair 1.

Differential LVPECL/ LVDS

DIF_REF1

Internal pull-down resistor1

Differential LVPECL/ LVDS, or single

ended LVCMOS/ LVTTL

REF_SEL

Input

Internal pull-down resistor1

Reference clock input selection. LVCMOS/LVTTL.

Logic 1 selects DIF_REF1/nDIF_REF1 inputs

Logic 0 selects DIF_REF0/nDIF_REF0 inputs

nDIF_REF0

Input

Biased to Vcc/2 2

Reference

clock input

pair 0.

Differential LVPECL/ LVDS

DIF_REF0

Internal pull-down resistor1

Differential LVPECL/ LVDS, or single

ended LVCMOS/ LVTTL

AUTO

Input

Internal pull-down resistor1

Automatic/manual reselection mode for clock input:

Logic 1 automatic reselection upon clock failure

(non-revertive)

Logic 0 manual selection only (using REF_SEL)

FIN_SEL1

FIN_SEL0

Input

Internal pull-UP resistor1

nput clock frequency selection. LVCMOS/LVTTL.

(For FIN_SEL1:0, see Table 3 on pg. 3.)

MR_SEL

Input

Internal pull-UP resistor1

M & R PLL divider ratio selection. LVCMOS/ LVTTL.

(For MR_SEL, see Table 4 on pg. 3.)

REF_ACK

Output

Reference Acknowledgement pin for input mux state;

outputs the currently selected reference input pair:

Logic 1 indicates nDIF_REF1, DIF_REF1

Logic 0 indicates nDIF_REF0, DIF_REF0

LOL

Output

Loss of Lock indicator output. 3

Logic 1 indicates loss of lock.

Logic 0 indicates locked condition.

Note 3: See LVCMOS Outputs in DC Characteristics on pg. 8.

NBW

Input

Internal pull-UP resistor1

Narrow Bandwidth enable. LVCMOS/LVTTL:

Logic 1 - Narrow loop bandwidth, R

IN = 2100k

Ω.

Logic 0 - Wide (normal) bandwidth, R

IN = 100k

Ω.

34, 35, 36

DNC

Do Not Connect.

Table 2: Pin Descriptions

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