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M2040 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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M2040 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 12 page  Product Data Sheet M2040 Datasheet Rev 1.0 Revised 28Jan2005 Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0 M2040 FREQUENCY TRANSLATION PLL WITH AUTOSWITCH Integrated Circuit Systems, Inc. GENERAL DESCRIPTION The M2040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in fault tolerant computing applications. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response. FEATURES ◆ Integrated SAW (surface acoustic wave) delay line; VCSO frequency of 400.00 or 533.3334 MHz;* outputs VCSO frequency or half; pin-configurable dividers ◆ Loss of Lock (LOL) indicator output ◆ Narrow Bandwidth control input (NBW Pin); Initialization (INIT) input overrides NBW at power-up ◆ Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL ◆ Automatic (non-revertive) reference clock reselection upon clock failure; controlled PLL slew rate ensures normal system operation during reference reselection ◆ Acknowledge pin indicates the actively selected reference input ◆ Dual differential LVPECL outputs ◆ Low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) ◆ Industrial temperature available ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package PIN ASSIGNMENT (9 x 9 mm SMT) Figure 1: Pin Assignment * Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM Figure 2: Simplified Block Diagram Example Input / Output Frequency Combinations Input (MHz) VCSO * (MHz) Output (MHz) 200.0000 400.0000 200.0000 213.3333 400.0000 266.6667 533.3334 266.6667 284.4444 533.3334 Table 1: Example Input / Output Frequency Combinations M 2 040 (Top V i ew) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND FIN_SEL0 MR_SEL REF_ACK LOL NBW VCC DNC DNC DNC Loop Filter PLL Phase Detector MR_SEL FIN_SEL1:0 R Div MUX 0 REF_SEL DIF_REF0 nDIF_REF0 1 Mfin Divider LUT Mfin Divider M Div FOUT0 nFOUT0 P Divider P_SEL NBW M / R Divider LUT DIF_REF1 nDIF_REF1 Auto Ref Sel 0 1 LOL Phase Detector REF_ACK AUTO INIT LOL FOUT1 nFOUT1 M2040 2 VCSO M2040 Frequency Translation PLL with AutoSwitch |
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