M2040 datasheet(5/12 Pages) ICST

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M2040 Datasheet Rev 1.0

5 of 12

Revised 28Jan2005

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M2040

FREQUENCY TRANSLATION PLL WITH AUTOSWITCH

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

PLL Operation

The M2040 is a complete clock PLL. It uses a phase

detector and configurable dividers to synchronize the

output of the VCSO with the selected reference clock.

The “M” divider (and the “Mfin” divider) divides the

VCSO output frequency, feeding the result into the plus

input of the phase detector.

The frequency input (“Mfin”) divider gives the device

the capability to be adapted for use with other input

frequencies.

The output of the “R” divider is fed into the minus input

of the phase detector. The phase detector compares its

two inputs. The phase detector output, filtered

externally, causes the VCSO to increase or decrease in

frequency as needed to phase- and frequency-lock the

VCSO to the reference input.

The value of M plus Mfin directly affects closed loop

bandwidth.

The relationship between the nominal VCSO center

frequency (Fvcso), the M divider, and the input

reference frequency (Fref_clk) is:

The M, R, and Mfin dividers can be set by pin

configuration using the input pins MR_SEL, FIN_SEL1, and

FIN_SEL0

P Divider and Outputs

The M2040 provides two differential LVPECL output

pairs: FOUT0 and FOUT1. One output divider (the “P”

divider) is used for both the FOUT0 and FOUT1 output

pairs. By using the P divider, the output frequency can

be the VCSO frequency (Fvcso) or 1/2 Fvcso.

The P_SEL pin selects the value for the P divider: logic 1

sets P to divide-by-2, logic 0 sets P to divide-by-1.

See Table 5, P Divider Selector Values

and Frequencies, on pg. 3.

When the P divider is included, the complete relation-

ship for the output frequency (Fout) is defined as:

Loss of Lock Indicator Output Pin

Under normal device operation, when the PLL is locked,

LOL

remains at logic 0. Under circumstances when the

VCSO cannot lock to the input (as measured by a

greater than 4 ns discrepancy between the feedback

and reference clock rising edges at the phase detector)

the LOL output goes to logic 1. The LOL pin will return

back to logic 0 when the phase detector error is less

than 2 ns. The loss of lock indicator is a low current

CMOS output.

Narrow Loop Bandwidth Control Pin (NBW Pin)

A Narrow Loop Bandwidth control pin (NBW pin) is

included to adjust the PLL loop bandwidth. In normal

(wide) bandwidth mode (NBW=0), the internal resistor

Rin is 100k

Ω. With the NBW pin asserted, the internal

resistor Rin is changed to 2100k

Ω. This lowers the loop

bandwidth by a factor of about 21 (2100 / 100) and

lowers the damping factor by about 4.6 (the square root

of 21), assuming the same loop filter components.

Fvcso

Fref_clk

MMfin

--------------------------

Fout

Fvcso

-------------------

Fref_clk

MMfin

--------------------------

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