M2040 Datasheet Rev 1.0

3 of 12

Revised 28Jan2005

M2040

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

Figure 3: Detailed Block Diagram

Mfin (Frequency Input) Divider Look-Up Table (LUT)

(“Mfin”).

M / R Divider Ratio Look-up Table (LUT)

divider values M and R, respectively.

Post-PLL Divider

The M2040 also features a post-PLL (P) divider for the

output clocks. It divides the VCSO frequency to produce

one of two selectable output frequencies (1/2 or 1/1 of

the VCSO frequency). That selected frequency appears

value for the P divider.

Phase

Locked

Loop

(PLL)

M2040

SAW Delay Line

Phase

Shifter

VCSO

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

OP_IN

nOP_IN

PLL

Phase

Detector

Loop Filter

Amplifier

External

Loop Filter

Components

MR_SEL

FIN_SEL1:0

R

Divider

MUX

0

REF_SEL

DIF_REF0

nDIF_REF0

1

Mfin Divider

LUT

M

Divider

FOUT0

nFOUT0

P Divider

P_SEL

NBW

R

IN

R

IN

M / R Divider

LUT

DIF_REF1

nDIF_REF1

Auto

Ref Sel

0

1

LOL

Phase

Detector

REF_ACK

AUTO

INIT

LOL

FOUT1

nFOUT1

2

FIN_SEL1:0

Mfin Value

11

1

10

4

01

8

00

32

Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)

MR_SEL

M R

Description

032 16

Used when Fin = 32/16 = 1/2 Fvcso

Note 1: Fvcso= Example 533.3334MHz in M2040-01-533.3334.

130 16

Used when Fin = 30/16 = 0.53334 Fvcso

Table 4: M / R Divider Ratio Look-up Table (LUT)

P_SEL

P Value

Example: M2040-533.3334

Output Frequency

(MHz)

1

2

266.6667

0

1

533.3334

Table 5: P Divider Selector Values and Frequencies