M2040 datasheet(4/12 Pages) ICST

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M2040 Datasheet Rev 1.0

4 of 12

Revised 28Jan2005

I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0

Integrated

Circuit

Systems, Inc.

M2040

FREQUENCY TRANSLATION PLL WITH AUTOSWITCH

Prod uct Data Sh eet

FUNCTIONAL DESCRIPTION

The M2040 is a PLL (Phase Locked Loop) based clock

generator that generates two output clocks

synchronized to one of two selectable input reference

clocks. An internal high “Q” SAW delay line provides a

low jitter clock output.

The device is pin-configured for feedback divider and

output divider values. Output is LVPECL compatible.

External loop filter component values set the PLL

bandwidth to optimize jitter attenuation characteristics.

The device features dual differential inputs with two

input selection modes: manual and automatic upon

clock failure. (The differential inputs are internally

configured for easy single-ended operation.)

The M2040 includes: a Loss of Lock (LOL) indicator, a

reference mux state acknowledge pin (REF_ACK), a

Narrow Bandwidth control input pin (NBW pin), and a

Power-on Initialization (INIT) input (which overrides

NBW=0

to facilitate acquisition of phase lock).

Hitless Switching (HS) is an optional feature that

provides a controlled output clock phase change during

a reference clock reselection. HS is triggered by a Loss

of Lock detection by the PLL.

Input Reference Clocks

Two clock reference inputs and a selection mux are

provided. Either reference clock input can accept a

differential clock signal (such as LVPECL or LVDS) or

a single-ended clock input (LVCMOS or LVTTL on the

non-inverting input).

A single-ended reference clock on the unselected

reference input can cause an increase in output

clock jitter. For this reason, differential reference

inputs are preferred; interference from a differential

input on the non-selected input is minimal.

Configuration of a single-ended input has been

facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,

with 50k

Ω to Vcc and 50kΩ to ground. The input clock

structure, and how it is used with either

LVCMOS/LVTTL inputs or a DC- coupled LVPECL

clock, is shown in Figure 4.

Figure 4: Input Reference Clocks

Differential Inputs

Differential LVPECL inputs are connected to both

reference input pins in the usual manner. The external

load termination resistors shown in Figure 4 (the 127

Ω

and 82

Ω resistors) is ideally suited for both AC and DC

coupled LVPECL reference clock lines. These provide

the 50

Ω load termination and the VTT bias voltage.

Single-ended Inputs

Single-ended inputs (LVCMOS or LVTTL) are

connected to the non-inverting reference input pin

(DIF_REF0 or DIF_REF1). The inverting reference input pin

(nDIF_REF0 or nDIF_REF1) must be left unconnected.

In single-ended operation, when the unused inverting

input pin (nDIF_REF0 or nDEF_REF1) is left floating (not

connected), the input will self-bias at VCC/2.

MUX

REF_SEL

VCC

50k

VCC

50k

LVCMOS/

LVTTL

LVPECL

50k

VCC

127

VCC

127

DIF_REF0

nDIF_REF0

DIF_REF1

nDIF_REF1

Ω

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