M2040 Datasheet Rev 1.0

7 of 12

Revised 28Jan2005

M2040

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

Hitless Switching Option

Hitless Switching is a device option that can be

specified at time of order. (Please contact ICS.) The

operation, the optional Hitless Switching (HS) function

will automatically place the device into narrow

bandwidth operation during reference reselection. This

provides a controlled output clock phase change while

the PLL is acquiring phase lock to a new reference

clock phase. The HS function is trigged by a loss of lock

event. Wide bandwidth is resumed once the PLL

relocks to the input reference. (When the NBW pin = 1,

the device operates in narrow bandwidth continually

and hence the HS mode does not apply).

The HS function is armed after the device locks to the

input clock reference (8 successive phase detector

clock cycles with LOL low). Once armed, HS is

triggered by detection at the phase detector of a single

phase error greater than 4 ns (rising edges).

Once triggered, the HS function narrows the loop band-

width until the PLL is locked to the selected reference (8

successive phase detector clock cycles with LOL low).

When pin AUTO = 1 (automatic reference reselection

mode) HS is used in conjunction with input reselection.

When AUTO = 0 (manual mode), HS will still occur upon

an input phase transient, however the clock input is not

reselected (this enables hitless switching when using an

external MUX for clock selection).

Power-Up Initialization Function (INIT Pin)

The initialization function provides a short-term override

of the narrow bandwidth mode when the device is

powered up in order to facilitate phase locking.

NBW

initialization function puts the PLL into wide bandwidth

mode until eight consecutive phase detector cycles

occur without a single LOL event. Once the eight valid

PLL locked states have occurred, the PLL bandwidth is

automatically reduced to narrow bandwidth mode.

bandwidth mode unconditionally.

External Loop Filter

The M2040 requires the use of an external loop filter

components. These are connected to the provided filter

pins (see Figure 5).

Because of the differential signal path design, the

implementation consists of two identical

complementary RC filters as shown in Figure 5, below.

Figure 5: External Loop Filter

PLL bandwidth is affected by the total “M” (feedback

divider) value, loop filter component values, and other

device parameters. See Table 7, External Loop Filter

Component Values, below.

PLL Simulator Tool Available

A free PC software utility is available on the ICS website

(www.icst.com). The M2000 Timing Modules PLL

Simulator is a downloadable application that simulates

PLL jitter and wander transfer characteristics. This

enables the user to set appropriate external loop

component values in a given application.

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

OP_IN

nOP_IN

6

7

5

49

8

Device Configuration

External Loop Filter Component Values

NBW

Nominal Performance Using These Values

F

VCSO

(MHz)

M

Divider

Value

R loop

C loop

R post

C post

PLL Loop

Bandwidth

Damping

Factor

Passband

533.333

30, 32

30

k

Ω

1.0

µF

33

k

Ω

100

pF

1

110

Hz

2.2

0.35

0

3 kHz

10

0.02

Table 7: External Loop Filter Component Values

Note 1: Recommended values for hitless switching. For PLL Simulator software, go to www.icst.com.

Note 3: This table does not apply to the 400 MHz VCSO option since the Kvco value is different.