AD7765 datasheet(24/32 Pages) AD

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AD7765

Rev. 0 | Page 24 of 32

CLOCKING THE AD7765

The AD7765 requires an external low jitter clock source. This

signal is applied to the MCLK pin. An internal clock signal

(ICLK) is derived from the MCLK input signal. The ICLK

controls the internal operation of the AD7765. The maximum

ICLK frequency is

20 MHz. To generate the ICLK

470

256

)

(

rms

The input amplitude also has an effect on these jitter figures.

For example, if the input level is 3 dB below full-scale, the

allowable jitter is increased by a factor of √2, increasing the first

example to 57.75 ps rms. This happens when the maximum

slew rate is decreased by a reduction in amplitude.

ICLK

= MCLK/2

For output data rates equal to those used in audio systems, a

12.288 MHz ICLK frequency can be used. As shown in Table 6,

output data rates of 96 kHz and 48 kHz are achievable with this

ICLK frequency.

Figure 38 and Figure 39 illustrate this point, showing the

maximum slew rate of a sine wave of the same frequency, but

with different amplitudes.

MCLK JITTER REQUIREMENTS

1.0

–1.0

0.5

–0.5

The MCLK jitter requirements depend on a number of factors

and are given by

)

(

)

(

SNR

OSR

rms

where:

OSR

= oversampling ratio = fICLK/ODR.

fIN

= maximum input frequency.

SNR(dB)

= target SNR.

Example 1

This example can be taken from Table 6, where:

ODR

= 156.25 kHz.

fICLK

= 20 MHz.

fIN

(max) = 78.625 kHz.

SNR

= 104 dB.

Figure 38. Maximum Slew Rate of Sine Wave

with Amplitude of 2 V p-p

1.0

–1.0

0.5

–0.5

rms

102

625

128

)

(

This is the maximum allowable clock jitter for a full-scale,

78.625 kHz input tone with the given ICLK and output

data rate.

Example 2

Take a second example for Table 6, where:

ODR

= 48 kHz.

fICLK

= 12.288 MHz.

fIN

(max) = 19.2 kHz.

SNR

= 109 dB.

Figure 39. Maximum Slew Rate of Same Frequency Sine Wave

with Amplitude of 1 V p-p

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