33689D datasheet(15/31 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33689

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS

Propagation Delay LIN to RXD (24)

Dominant State (LIN LOW to RXD LOW)

Recessive State (LIN HIGH to RXD HIGH)

Symmetry (

tRDOM - tRREC)

tRDOM

tRREC

tRSYM

—

-2.0

3.0

—

6.0

2.0

µs

Bus Wake-Up Deglitcher (Sleep and Stop Modes) (25)

tPROPWL

µs

Bus Wake-Up Event Reported

From Sleep Mode (26)

From Stop Mode (27)

tWU

—

µs

Notes

24.

Measured between LIN signal threshold VINL or VINH and 50% of RXD signal.

25.

See Figures 9 and 10, page 18.

26.

tWU is typically 2 internal clock cycles after a LIN rising edge is detected. In Sleep Mode, the measurement is done without a capacitor

connected to the regulator. The delay is measured between the VSUP/2 rising edge of the LIN bus and when VDD reaches 3.0 V. The

VDD rise time is strongly dependent upon the decoupling capacitor at VDD pin. See Figure 9, page 18.

27.

tWU is typically 2 internal clock cycles after a LIN rising edge is detected. In Stop Mode, the delay is measured between the VSUP/2

rising edge of the LIN bus and the falling edge of the INT pin. See Figure 10, page 18.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V

≤ V

SUP ≤ 18 V, - 40°C ≤ T

A ≤ 125°C, GND = 0.0 V unless otherwise noted.

Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

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