33991 datasheet(12/36 Pages) FREESCALE

12 / 36 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33991

33991 SPI INTERFACE AND PROTOCOL DESCRIPTION

INTRODUCTION

33991 SPI INTERFACE AND PROTOCOL DESCRIPTION

INTRODUCTION

The SPI interface has a full duplex, three-wire

synchronous, 16-bit serial synchronous interface data

transfer and four I/O lines associated with it: (SI, SO, SCLK,

and CS). The SI/SO pins of the 33991 follows a first in / first

out (D15 / D0) protocol with both input and output words

transferring the most significant bit first. All inputs are

compatible with 5.0 V CMOS logic levels.

DETAILED SIGNAL DESCRIPTIONS

CHIP SELECT (CS)

The Chip Select (CS) pin enables communication with the

master device. When this pin is in a logic [0] state, the 33991

is capable of transferring information to, and receiving

information from, the master. The 33991latches data in from

the Input Shift registers to the addressed registers on the

rising edge of CS. The output driver on the SO pin is enabled

when CS is logic [0]. When CS is logic high, signals at the

SCLK and SI pins are ignored; the SO pin is tri-stated (high

impedance). CS will only be transitioned from a logic [1] state

to a logic [0] state when SCLK is a logic [0]. CS has an

internal pull-up (lup) connected to the pin as specified in the

Control I/O Table.

SERIAL CLOCK (SCLK)

SCLK clocks the Internal Shift registers of the

33991device. The Serial Input (SI) pin accepts data into the

Input Shift register on the falling edge of the SCLK signal

while the Serial Output pin (SO) shifts data information out of

the SO Line Driver on the rising edge of the SCLK signal. It is

important the SCLK pin be in a logic [0] state whenever the

CS makes any transition. SCLK has an internal pull down

(Idwn), specified in the Control I/O Table. When CS is logic

[1], signals at the SCLK and SI pins are ignored; SO is tri-

stated (high impedance). See the Data Transfer Timing

diagrams in Figures 2 and 3.

SERIAL INPUT (SI)

This pin is the input of the Serial Peripheral Interface (SPI).

Serial Input (SI) information is read on the falling edge of

SCLK. A 16-bit stream of serial data is required on the SI pin,

beginning with the most significant bit (MSB). Messages not

multiples of 16 bits (e.g. daisy chained device messages) are

ignored. After transmitting a 16-bit word, the CS pin has to be

deasserted (logic [1]) before transmitting a new word. SI

information is ignored when CS is in a logic high state.

SERIAL OUTPUT (SO)

The Serial Output (SO) data pin is a tri-stateable output

from the Shift register. The Status register bits will be the first

16-bits shifted out. Those bits are followed by the message

bits clocked in FIFO, when the device is in a daisy chain

connection, or being sent words of 16-bit multiples. Data is

shifted on the rising edge of the SCLK signal. The SO pin will

remain in a high impedance state until the CS pin is put into

a logic low state.

FUNCTIONAL DESCRIPTION

This section provides a description of the 33991 SPI

behavior. To follow the explanations below, please refer to

the timing

diagrams shown in Figures 4 and 5.

Table 4. Data Transfer Timing

Description

CS (1-to-0)

SO pin is enabled

CS (0-to-1)

33991 configuration and desired output states are transferred and executed according to the data in

the Shift registers.

Will change state on the rising edge of the SCLK pin signal.

Will accept data on the falling edge of the SCLK pin signal

33991 Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc

33991 Datasheet(HTML) 12 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL