May 1994

18

Philips Semiconductors

Preliminary specification

Stereo filter and codec

SAA2003

Table 12 Fade rate in slow and fast modes.

IEC 958 output

The IECOP pin provides an output signal in accordance with the IEC 958/SPDIF digital audio interface format.

The function of the IECOP pin is programmed by bit 3 of the codec extended settings register; see Table 13.

Table 13 IECOP pin control.

The IECOP output will only function when the SAA2003 is in decode mode. The IECOP cannot be used when SAA2013

is present in the system, unless the SAA2013 is in sleep mode. The IECOP output is disabled and set to high impedance

by a reset.

L3 bus

The L3 bus is a three-wire clock synchronous data bus common to all ICs in the DCC chip-set. It consists of the L3MODE,

L3CLK and L3DATA connections. The bus has two operating modes:

• Addressing mode; selects the IC for communication and sets type of transfer.

• Data mode; is used to send and receive data and control settings.

The L3MODE and L3CLK lines are driven by the system microcontroller and L3DATA is a bi-directional line. LTCNT0

and LTCNT1 must be left unconnected when L3 mode is used.

For normal use in L3 mode, LTCNT0 and LTCNT1 are held HIGH by internal pull-up resistors. The SAA2003 responds

to serial addresses as shown in Table 14.

Table 14 SAA2003 serial addresses.

Note

1. D0 and D1 are interpreted as LTCNT0 and LTCNT1 respectively. These two signals control the operation of the

interface as given in Table 15.

MODE

P3

P2

P1

P0

TIME PER STEP (ms)

TIME FOR 256 STEPS (ms)

32 kHz

44.1 kHz

48 kHz

32 kHz

44.1 kHz

48 kHz

Fast

−−−−

31.2

µs

22.7

µs

20.8

µs

8.0

5.8

5.3

Slow

0000

1.0

0.997

1.0

256

255

256

Slow

0001

2.0

1.994

2.0

512

511

512

Slow

0011

4.0

3.988

4.0

1024

1021

1024

Slow

0111

8.0

7.980

8.0

2048

2043

2048

Slow

1111

16.0

15.96

16.0

4096

4087

4096

A3

A2

A1

A0

D3

D2

D1

D0

IECOP FUNCTION

00010

X

X

X

IEC 958 (default)

00011

X

X

X

D2

D3

D4

D5

D6

D7

X

X

000100