SAA2003 datasheet(4/44 Pages) PHILIPS

4 / 44 page

May 1994

Philips Semiconductors

Preliminary speciﬁcation

Stereo ﬁlter and codec

SAA2003

PINNING

SYMBOL

DESCRIPTION

TYPE

FDAI

ﬁltered data input from SAA2013

FDCL

ﬁltered data bit clock

FDWS

ﬁltered data word select

CLK22

22.5792 MHz buffered clock output

X22OUT

22.5792 MHz crystal output

X22IN

22.5792 MHz crystal input

VDD2

supply voltage (clock oscillator)

−

VSS2

supply ground (clock oscillator)

−

X24OUT

24.576 MHz crystal output

X24IN

24.576 MHz crystal input

CLK24

24.576 MHz buffered clock output

SLEEP

sleep mode; device inactive

RESET

device reset

L3DATA

3-wire interface; serial data

I/O

L3CLK

3-wire interface; bit clock

L3MODE

3-wire interface; mode control

LTCNT0

LT interface; control bit 0

LTCNT1

LT interface; control bit 1

TEST0

test mode select

TEST1

test mode select

URDA

unreliable data ﬂag from drive processor

SBDIR

sub-band data direction

SBDA

sub-band serial data

I/O

SBCL

sub-band bit clock

I/O

SBWS

sub-band word select

I/O

SBEF

sub-band error ﬂag from drive processor

VSS1

digital supply ground

−

VDD1

digital supply voltage

−

IECOP

IEC 958 digital audio output

DEEMDAC

DAC control or general purpose output

ATTDAC

DAC control or general purpose output

MUTEDAC

DAC control or general purpose output

SD2

serial audio data to DAC

SD1

serial audio data to/from DAIO and DAC

I/O

SCK

serial audio data bit clock

I/O

serial audio data word select

I/O

X256

master audio clock from external source

FS256

master audio clock at 256 times sample frequency

VDD3

supply voltage (FS256)

−

VSS3

supply ground (FS256)

−

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