SAA6721 datasheet(44/72 Pages) PHILIPS

44 / 72 page

1999 May 11

Philips Semiconductors

Preliminary speciﬁcation

SXGA RGB to TFT graphics engine

SAA6721E

8.2.2

CLOCK DIVIDER

The pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval

from 1.5 to 10.5. All further dividing ratios are in steps of 1.0; see Fig.12 and Table 9.

Programming of the clock dividers must be done using the registers 26 to 32. It is necessary that the clock dividers must

be disabled before programming and be enabled afterwards. This can be done with pre_div_enable and

post_div_enable.

Table 9

Clock divider programming

RATIO

P-COUNTER

(HEX)

N-COUNTER

(HEX)

N-OFFSET

COUNTER (HEX)

HALF CLK

1.5

2.0

2.5

3.0

3.5

Fig.11 Clock generator.

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MHB251

PLL

× 32

PRE-DIVIDER

POST-DIVIDER

÷ 2

MCLKO

PCLK

MCLKI

CLK

Fig.12 Clock waveforms.

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MHB252

CLK

CLK/4

CLK/5

CLK/4.5

CLK/5.5

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