SAA6721 datasheet(13/72 Pages) PHILIPS

13 / 72 page

1999 May 11

Philips Semiconductors

Preliminary speciﬁcation

SXGA RGB to TFT graphics engine

SAA6721E

Notes

1. Generally all inputs are 5 V tolerant TTL inputs. All outputs are CMOS, except the memory interface ports, which are

LVTTL compatible.

2. Connect to ground when not using the JTAG controller.

n.c.

L18

−−

not connected

n.c.

P20

−−

not connected

n.c.

R20

−−

not connected

n.c.

−−

not connected

n.c.

−−

not connected

n.c.

−−

not connected

n.c.

U14

−−

not connected

n.c.

U20

−−

not connected

n.c.

V20

−−

not connected

n.c.

−−

not connected

n.c.

W15

−−

not connected

SYMBOL

PORT

I/O(1)

DESCRIPTION

FUNCTIONAL DESCRIPTION

7.1

Data path

Input video data is sampled either as RGB data in single

pixels from only one ADC or in double pixels in interleaved

format from two ADCs. Alternatively the input interface can

sample interlaced or non-interlaced YUV data. The clock

for sampling the data will always be provided from external

circuitry. The video stream will be adapted from the input

frame rate to the output frame rate needed by the panel.

Therefore a frame buffer built of SDRAMs or SGRAMs is

used. If the panel supports the incoming frame rate from

the RGB port, the adaption can be done without external

memory. If the video stream is in interlaced format the

memory interface activates its de-interlacing unit.

If zooming must be performed the upscaler behind the

memory interface will be enabled. For downscaling the

downscaler in front of the memory interface in the data

path will be used. A colour correction can be done via a

look-up table. The resulting video stream can now be

positioned elsewhere in the output data stream by the

panning unit. If an external OSD controller is embedded

into the system, its OSD window will be put into the video

stream by the OSD overlay port. Additionally the internal

OSD will be inserted in the next stage. The temporal

dithering allows true colour pictures to be displayed on

high colour panels. The output interface provides the

timing and control signals necessary for the connected

panel.

7.2

System clocks

7.2.1

INPUT INTERFACE CLOCK (VCLK)

This clock is used for sampling the incoming RGB or YUV

data stream. In RGB mode this clock varies from

25 to 150 MHz in single ADC mode. If two ADCs are used

the RGB input clock is between 12.5 and 75 MHz. In YUV

mode the clock lies in the range of approximately 30 MHz.

The clocks are generated from external devices.

The RGB clock can be generated by the external ADCs or

an external video PLL. The YUV clock must be generated

by the video decoder which also provides the YUV video

data.

7.2.2

MEMORY INTERFACE CLOCK (MCLKI)

The memory clock is the synchronous clock for the

external frame buffer. Depending on the bandwidth

needed by the application, and the connected SDRAM or

SGRAM devices, the clock varies from 83 to 125 MHz.

It can be generated internally by the PLL from the system

clock (CLK), or by an external quartz oscillator.

If the internal PLL is used, the memory clock frequency

can be derived from the following formula:

Where N = pre-divider ratio and f_system = clock at

pin CLK.

f_memory

f_system

------------------------

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