SAA6721 datasheet(21/72 Pages) PHILIPS

21 / 72 page

1999 May 11

Philips Semiconductors

Preliminary speciﬁcation

SXGA RGB to TFT graphics engine

SAA6721E

7.9.2

DOWNSCALING

The downscaling engine is used for reducing the incoming

RGB data stream, i.e. for displaying high resolution input

frames on panels with a smaller resolution. The scaling

ratio can be programmed independently for both horizontal

and vertical downscaling units. The algorithm uses pixel

accumulation, achieving a minimum scaling factor of 1

⁄64.

SYSTEM DESCRIPTION

8.1

Programming registers

The SAA6721E is a highly integrated device with many

features. To get the desired functionality and performance

it must be programmed correctly. In general, before

programming, the device must be switched to the internal

reset state to prevent unwanted functions while changing

the registers.

After writing to all registers the internal reset can be

released. There are some registers (mainly offset

counters) that can be changed during data processing

without an internal reset. All accesses to the on screen

display can be done during data processing.

Table 6

I2C-bus device address

Bit SAD = 0 the address is 74H, while bit SAD = 1 the

address is 76H.

Table 7 shows the programming model.

MSB

LSB

011101

SAD

R/W

Table 7

Programming register overview

ADDRESS R/W

State

reserved

R/W iic_test_register[7 to 0]

intr

RGB mode detection

pos_

vsync

pos_

hsync

no_

vsync

no_

hsync

v_lines[7 to 0]

v_lines[10 to 8]

h_clocks[7 to 0]

h_clocks[11 to 8]

RGB auto-adjustment

ref_line[7 to 0]

ref_line[10 to 8]

ref_pixel[7 to 0]

ref_pixel[11 to 8]

ref_colour[7 to 0]

ref_pixel_red[7 to 0]

ref_pixel_green[7 to 0]

ref_pixel_blue[7 to 0]

black_lines[7 to 0]

black_pixels[7 to 0]

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