SST85LD0256 datasheet(63/73 Pages) SST

63 / 73 page

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SST85LD0128 / SST85LD0256 / SST85LD0512

S71319-03-000

2/07

13.2 AC Characteristics

FIGURE

13-1: AC Input/Output Reference Waveforms

13.2.1 Host Side Interface I/O Input (Read) Timing Specification

Note: The maximum load on IOCS16# is 1 LSTTL with 50pF total load.

All AC specifications are guaranteed by design.

FIGURE

13-2: Host Side Interface I/O Read Timing Diagram

TABLE

13-7: Host Side Interface I/O Read Timing

Symbol

Parameter

Min

Max

Units

TSU (IORD#)

Data Setup before IORD#

TH (IORD#)

Data Hold following IORD#

TW (IORD#)

IORD# Width Time

TSUA (IORD#)

Address Setup before IORD#

THA (IORD#)

Address Hold following IORD#

TDF IOCS16#(ADR) IOCS16# Delay Falling from Address

TDR IOCS16#(ADR) IOCS16# Delay Rising from Address

T13-7.0 1319

1319 F02.0

REFERENCE POINTS

OUTPUT

INPUT

VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference

points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1319 F03.0

TDR IOCS16#(ADR)

TDF IOCS16#(ADR)

THA (IORD#)

TH (IORD#)

TSUA (IORD#)

SU (IORD#)

TW (IORD#)

Valid Address

IORD#

IOCS16#

D15-D0

DOUT

Note: Valid Address consists of signals CS1FX#, CS3FX# and A2-A0.

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