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SST85LD0256 Datasheet(PDF) 67 Page - Silicon Storage Technology, Inc

Part # SST85LD0256
Description  NANDrive
PDF  73 Pages
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST85LD0256 Datasheet(HTML) 67 Page - Silicon Storage Technology, Inc

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SST85LD0128 / SST85LD0256 / SST85LD0512
©2007 Silicon Storage Technology, Inc.
S71319-03-000
2/07
67
FIGURE
13-7: Host Terminates a Multi-word DMA Data Transfer
13.2.4 External Flash Media Bus I/O Timing Specifications
Note: All AC specifications are guaranteed by design.
TABLE 13-10: External Flash Media Bus Timing Parameters
Symbol
Parameter
Min
Max
Units
TCLS
FCLE Setup Time
20
-
ns
TCLH
FCLE Hold Time
40
-
ns
TCS
FCE# Setup Time
40
-
ns
TCH
FCE# Hold Time for Command/Data Write Cycle
40
-
ns
TCHR
FCE# Hold Time for Sequential Read Last Cycle
-
40
ns
TWP
FWE# Pulse Width
20
-
ns
TWH
FWE# High Hold Time
20
-
ns
TWC
Write Cycle Time
40
-
ns
TALS
FALE Setup Time
20
-
ns
TALH
FALE Hold Time
40
-
ns
TDS
FAD[15:0] Setup Time
20
-
ns
TDH
FAD[15:0] Hold Time
20
-
ns
TRP
FRE# Pulse Width
20
-
ns
TRR
Ready to FRE# Low
40
-
ns
TREA
FRE# Data Setup Access Time
20
-
ns
TRC
Read Cycle Time
40
-
ns
TREH
FRE# High Hold Time
30
-
ns
TRHZ
FRE# High to Data Hi-Z
5
-
ns
T13-10.0 1319
Write DQ15-0
Read DQ15-0
IORD#/IOWR
DMACK#
DMARQ
CS1FX#/CS3FX#
1319 F08.0
T0
TD
TK
TE
TN
TZ
TJ
TF
TH
TG
Note: 1. To terminate the transmission of a data burst, the host should negate DMACK# within the
specified time after a IORD# or IOWR# pulse. No further IORD# or IOWR# pulses shall be
asserted for this burst.
2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted
and wait for the host to reassert DMACK# or may negate DMARQ at any time after detecting
that DMACK# has been negated.



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