AD5674 datasheet(23/32 Pages) AD

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Data Sheet

AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 23 of 32

THEORY OF OPERATION

DAC

The AD5674/AD5674R/AD5679/AD5679R are 16-channel,

12-/16-bit, serial input, voltage output DAC with an internal

reference. The device operates from supply voltages of 2.7 V to

5.5 V. Data is written to the AD5674/AD5674R/AD5679/

AD5679R in a 24-bit word format via a 3-wire serial interface.

The AD5674/AD5674R/AD5679/AD5679R incorporate a POR

circuit to ensure that the DAC output powers up to a known

output state. The device also has a software power-down mode

that reduces the typical current consumption to 2 µA.

TRANSFER FUNCTION

The internal reference is on by default.

The gain of the output amplifier can be set to ×1 or ×2 using the

span set pin (GAIN). When the GAIN pin is tied to GND, all

16 DAC outputs have a span from 0 V to VREF. When the GAIN

pin is tied to VLOGIC, all 16 DACs output a span of 0 V to

2 × VREF.

DAC ARCHITECTURE

The AD5674/AD5674R/AD5679/AD5679R implement a

segmented string DAC architecture with an internal output

buffer. Figure 57 shows the internal block diagram.

Figure 57. Single DAC Channel Architecture Block Diagram

Figure 58. Resistor String Structure

Figure 58 shows the resistor string structure. The code loaded to

the DAC register determines the node on the string where the

voltage is tapped off and fed into the output amplifier. The voltage

is tapped off by closing one of the switches and connecting the

string to the amplifier. Because each resistance in the string has

the same value, R, the string DAC is guaranteed monotonic.

Internal Reference

The AD5674R/AD5679R on-chip reference is enabled at power-

up, but can be disabled via a write to the control register. See the

Internal Reference Setup section for details.

The AD5674R/AD5679R have a 2.5 V, 2 ppm/°C reference,

resulting in a full-scale output of 2.5 V or 5 V, depending on the

state of the GAIN pin. The internal reference associated with

the device is available at the VREF pin. This buffered reference

is capable of driving external loads of up to 15 mA.

Output Amplifiers

The output buffer amplifier generates rail-to-rail voltages on its

output. The actual range depends on the value of VREF, the gain

setting, the offset error, and the gain error.

The output amplifiers can drive a load of 1 kΩ in parallel with

10 nF to GND. The slew rate is 0.8 V/µs, with a typical ¼ to ¾

scale settling time of 6 µs.

SERIAL INTERFACE

The AD5674/AD5674R/AD5679/AD5679R use a 3-wire serial

interface (SYNC, SCLK, and SDI, compatible with SPI, QSPI™,

and MICROWIRE interface standards, as well as most digital

signal processors (DSPs). See Figure 2 for a timing diagram of a

typical write sequence. The

AD5674/AD5674R/AD5679/AD5679R contain an SDO pin to

allow the user to daisy-chain multiple devices together (see the

Daisy-Chain Operation section) or for readback.

Input Shift Register

The input shift register of the

AD5674/AD5674R/AD5679/AD5679R is 24 bits wide. Data is

loaded MSB first (DB23), and the first four bits are the command

bits, C3 to C0 (see Table 10, followed by the 4-bit DAC address

bits, A3 to A0 (see Table 11), and finally, the 16-bit data-word.

The data-word is comprised of a 16-bit input code for the AD5679

and AD5679R, and a 12-bit code followed by four zeroes, or

don’t care bits, for the AD5674 and AD5674R models (see

Figure 60 and Figure 59). These data bits are transferred to the

input register on the 24 falling edges of SCLK and are updated

on the rising edge of SYNC.

Commands execute on individual DAC channels, combined DAC

channels, or on all DACs, depending on the DAC address bits

selected.

INPUT

2.5V

REF

DAC

RESISTOR

STRING

REF (+)

REF (–)

VREF

VOUTx

GND

GAIN

(GAIN = 1 OR 2)

TO OUTPUT

AMPLIFIER

VREF

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