AD5673R/AD5677R

Data Sheet

Rev. 0 | Page 8 of 31

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications are TJ = −40°C to +125°C, unless otherwise noted. See Figure 2 and Figure 3.

Table 5.

Parameter1

Min

Typ

Max

Unit

Description

t1

2.5

µs

SCL cycle time

t2

0.6

µs

SCL high time

t3

1.3

µs

SCL low time

t4

0.6

µs

Start or repeated start hold time

t5

100

ns

Data setup time

t62

0

0.9

µs

Data hold time

t7

0.6

µs

Repeated start setup time

t8

0.6

µs

Stop condition setup time

t9

1.3

µs

Bus free time between a stop condition and a start condition

t103

20 + 0.1CB

300

ns

Rise time of SCL and SDA when receiving

t113, 4

20 + 0.1CB

300

ns

Fall time of SCL and SDA when transmitting or receiving

t12

20

ns

LDAC pulse width

t13

400

ns

SCL rising edge to LDAC rising edge

t14

8

ns

RESET minimum pulse width low, 1.62 V ≤ VLOGIC ≤ 2.7 V

10

ns

RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V

t15

115

ns

RESET activation time, 1.62 V ≤ VLOGIC ≤ 2.7 V

115

ns

RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V

tSP5

0

50

ns

Pulse width of suppressed spike

CB4

400

pF

Capacitive load for each bus line

Update Rate

400

kHz

Fast mode

100

kHz

Standard mode

1

See Figure 2.

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the

SCL falling edge.

3

t10 (rise time) and t11 (fall time) are measured from 0.3 × VDD to 0.7 × VDD.

4

CB is the total capacitance of one bus line in pF.

5

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. Not shown in Figure 2 or Figure 3.

Timing Diagrams

SCL

SDA

t1

t3

LDAC1

LDAC2

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

t4

t6

t5

t7

t8

t2

t13

t4

t11

t10

t12

t12

t9

Figure 2. 2-Wire Serial Interface Timing Diagram

RESET

VOUTx

t14

t15

Figure 3. RESET Timing Diagram