AD5673R/AD5677R

Data Sheet

Rev. 0 | Page 10 of 31

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

VOUT0

2

VDD

3

SCL

4

A0

5

A1

6

GAIN

7

VOUT7

17 LDAC

18 VLOGIC

19 SDA

20 RESET

21 VREF

16 GND

15 GND

TOP VIEW

(Not to Scale)

AD5673R/AD5677R

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE

TIED TO GND.

Figure 4. Pin Configuration Diagram

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VOUT0

Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.

2

VDD

Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in

parallel with a 0.1 µF capacitor to GND.

3

SCL

Serial Clock Line. In conjunction with the SDA line, the SCL pin clocks data into or out of the 24-bit input shift

register.

4

A0

Address Input. Sets the first LSB of the 7-bit slave address.

5

A1

Address Input. Sets the second LSB of the 7-bit slave address.

6

GAIN

Span Set. When the GAIN pin is tied to GND, all 16 DAC outputs have a span from 0 V to VREF. If the GAIN pin is tied

to VLOGIC, all 16 DACs output a span of 0 V to 2 × VREF.

7

VOUT7

Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.

8

VOUT6

Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.

9

VOUT5

Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.

10

VOUT4

Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.

11

VOUT15

Analog Output Voltage from DAC 15. The output amplifier has rail-to-rail operation.

12

VOUT14

Analog Output Voltage from DAC 14. The output amplifier has rail-to-rail operation.

13

VOUT13

Analog Output Voltage from DAC 13. The output amplifier has rail-to-rail operation.

14

VOUT12

Analog Output Voltage from DAC 12. The output amplifier has rail-to-rail operation.

15, 16

GND

Ground Reference Point for All Circuitry on the Device.

17

LDAC

Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing Pin 17 low updates any or all

DAC registers when the input registers have new data, which simultaneously updates all DAC outputs. Pin 17 can also

be tied permanently low.

18

VLOGIC

Digital Power Supply. The voltage on Pin 18 is specified in Table 2 and Table 3 within the power requirements

parameter section.

19

SDA

Serial Data Input. In conjunction with the SCL line, Pin 19 clocks data into or out of the 24-bit input shift register.

SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor.

20

RESET

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.

When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending

on the model in use.

21

VREF

Reference Output Voltage. When using the internal reference, VREF is the reference output pin. Pin 21 is the

reference output by default.

22

VOUT11

Analog Output Voltage from DAC 11. The output amplifier has rail-to-rail operation.

23

VOUT10

Analog Output Voltage from DAC 10. The output amplifier has rail-to-rail operation.

24

VOUT9

Analog Output Voltage from DAC 9. The output amplifier has rail-to-rail operation.

25

VOUT8

Analog Output Voltage from DAC 8. The output amplifier has rail-to-rail operation.