16-Channel, 12-/16-Bit nanoDAC+ with

2 ppm/°C Voltage Reference TC, I2C Interface

Data Sheet

AD5673R/AD5677R

Rev. 0

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FEATURES

High performance

High relative accuracy (INL): ±4 LSB maximum at 16 bits

(AD5677R only)

TUE: ±0.14% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.06% of FSR maximum

Low drift, 2.5 V voltage reference TC: 2 ppm/°C typical

40 mA short-circuit current

Wide operating ranges

−40°C to +125°C temperature range

2.7 V to 5.5 V power supply range

Simplified implementation

User selectable gain of 1 or 2 (GAIN pin)

1.8 V logic compatibility

400 kHz I2C-compatible serial interface

28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

APPLICATIONS

Optical transceivers

Base station power amplifiers

Process control (programmable logic controller (PLC)

input/output cards)

Industrial automation

Data acquisition systems

GENERAL DESCRIPTION

The AD5673R/AD5677R are low power, 16-channel, 12-/16-bit,

buffered voltage output, digital-to-analog converters (DACs)

that include a 2.5 V, 2 ppm/°C internal reference (enabled by

default), and a gain select pin, resulting in a full-scale output of

2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a

single, 2.7 V to 5.5 V supply range and are guaranteed monotonic

by design. The AD5673R/AD5677R are available in a 28-lead lead

frame chip scale package (LFCSP) and incorporate a power-on

reset (POR) circuit that ensures that the DAC outputs power up

to and remain at zero scale or midscale until a valid write. The

AD5673R/AD5677R contain a power-down mode that reduces

the current consumption to 2 µA typical.

Table 1. Octal and 16-Channel nanoDAC+® Devices

Channel

Count

Interface

Reference

16-Bit

12-Bit

8

SPI

Internal

AD5676R

AD5672R

External

AD5676

Not applicable

I2C

Internal

AD5675R

AD5671R

16

SPI

Internal

AD5679R

AD5674R

External

AD5679

AD5674

I2C

Internal

AD5677R

AD5673R

PRODUCT HIGHLIGHTS

1. High channel density: 16 channels in 4 mm × 4 mm LFCSP.

2. High relative accuracy (INL).

AD5673R (12-bit): ±1 LSB maximum.

AD5677R (16-bit): ±4 LSB maximum.

3. Low drift, 2.5 V, on-chip reference.

FUNCTIONAL BLOCK DIAGRAM

INPUT

REGISTER

A0

A1

GND

LDAC

SCL

AD5673R/AD5677R

RESET

2.5V REF

VOUT0

STRING

DAC 0

BUFFER

GAIN

POWER-DOWN

LOGIC

POWER-ON

RESET

VLOGIC

GAIN

×1/×2

VDD

VREF

SDA

VOUT14

VOUT15

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING

DAC 14

STRING

DAC 15

BUFFER

BUFFER

Figure 1.