AD9082

Data Sheet

Rev. C | Page 16 of 36

TIMING SPECIFICATIONS

For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply, unless otherwise noted.

Table 18.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SERIAL PORT INTERFACE (SPI) WRITE OPERATION

Maximum SCLK Clock Rate

fSCLK, 1/tSCLK

33

MHz

SCLK Clock High

tPWH

SCLK = 33 MHz

8

ns

SCLK Clock Low

tPWL

SCLK = 33 MHz

8

ns

SDIO to SCLK Setup Time

tDS

4

ns

SCLK to SDIO Hold Time

tDH

4

ns

CSB to SCLK Setup Time

tS

4

ns

SCLK to CSB Hold Time

tH

4

ps

SPI READ OPERATION

LSB First Data Format

Maximum SCLK Clock Rate

fSCLK, 1/tSCLK

33

MHz

SCLK Clock High

tPWH

8

ns

SCLK Clock Low

tPWL

8

ns

MSB First Data Format

Maximum SCLK Clock Rate

fSCLK, 1/tSCLK

15

MHz

SCLK Clock High

tPWH

30

ns

SCLK Clock Low

tPWL

30

ns

SDIO to SCLK Setup Time

tDS

4

ns

SCLK to SDIO Hold Time

tDH

4

ns

CSB to SCLK Setup Time

tS

4

ns

SCLK to SDIO Data Valid Time

tDV

20

ns

SCLK to SDO Data Valid Time

tDV_SDO

20

ns

CSB to SDIO Output Valid to High-Z

tZ

20

ns

CSB to SDO Output Valid to High-Z

tZ_SDO

20

ns

Timing Diagrams

tS

tDS

tPWH

tPWL

tDH

tSCLK

tH

R/W

A15

A14

A0

D7

D6 D1

D0

CSB

SCLK

SDIO

Figure 2. Timing Diagram for 3-Wire Write Operation

tS

tDS

tPWH

tPWL

tDH

tSCLK

tDV

tZ

CSB

SCLK

SDIO

R/W A14 A2

A1

A0

D7

D6 D1 D0

Figure 3. Timing Diagram for 3-Wire Read Operation

tPWH

tPWL

tS

tSCLK

tDS

tDH

tDV_SDO

tZ_SDO

CSB

SCLK

SDIO

SDO

D7

D6 D1 D0

R/W A14 A2

A1

A0

Figure 4. Timing Diagram for 4-Wire Read Operation