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AD2426 Datasheet(PDF) 13 Page - Analog Devices |
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AD2426 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 38 page ![]() Rev. F | Page 13 of 38 | November 2023 AD2426/AD2427/AD2428 Table 6. I2C Port Timing Parameter Min Typ Max Unit Timing Requirements fSCL SCL Clock Frequency 0 400 kHz tSCLH SCL Pulse Width High 0.6 μs tSCLL SCL Pulse Width Low 1.3 μs tSCS Start and Repeated Start Condition Setup Time 0.6 μs tSCH Start Condition Hold Time 0.6 μs tSPS Stop Condition Hold Time 0.6 μs tDS Data Setup Time 100 ns tDH Data Hold Time 0.0 0.9 μs tSCLR SCL Rise Time 300 ns tSCLF SCL Fall Time 300 ns tSDR SDA Rise Time 300 ns tSDF SDA Fall Time 300 ns tBFT Bus-Free Time Between Stop and Start 1.3 μs Figure 10. I2C Port Timing S Sr SDA SCL P S tSCLR tSCLF tSCLL tSCH tDH tSCLH tDS tSPS tBFT tSCS tSDR tSDF tSCS tSCH |
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