AD2426 datasheet(29/38 Pages) AD

29 / 38 page

AD2426/AD2427/AD2428

Rev. F

Page 29 of 38

November 2023

Peripheral Supply Current

Peripheral components that are external to the transceiver also

can be supplied through the voltage regulator outputs of VVOUT1

and VVOUT2. VVOUT1 can supply the current specified as IVEXT1 to

external devices. VVOUT2 can supply the current specified as

IVEXT2 to external devices.

When bus powered, peripheral supply current draw has a direct

impact on other nodes in the system. It is important to stay

within the thermal package limits and not exceed the specifica-

tion limits of IVSSN and VVIN in any of the A

2B bus nodes.

Digital Logic Supply Current

The digital logic supply current IDVDD is a combination of static

current consumption and digital TX/RX current.

A2B Bus TX/RX Current

The level of A2B bus activity directly influences current con-

sumption on both the LVDS transceivers related to A2B

transmitter and receiver processing.

LVDS Transmitter and Receiver Supply Currents

The current ITRXVDD depends on ITXVDD and IRXVDD at 100% activ-

ity level and A2B bus activity:

• Downstream LVDS transceiver current

•B transceiver IBTXVDD LVDS TX current results from

downstream TX activity level of the current node.

•A transceiver IARXVDD LVDS RX current results from

downstream activity level of the previous node.

• Upstream LVDS transceiver current

•A transceiver IATXVDD LVDS TX current results from 

A side upstream activity level of the current node.

•B transceiver IBRXVDD LVDS RX current results from

upstream activity level of the next in line node.

Downstream/Upstream Activity Level

The activity level for downstream data of TRX B is determined

by the following:

• Header bits for downstream. A2B systems use 64 down-

stream header bits referred to as a synchronization control

frame (SCF).

• The number of downstream data bits transmitted in 

a node = the number of downstream transmitted slots ×

(bits per slot + parity bit) where the parity bit = 1. The

number of downstream transmitted slots does not include

the locally consumed slots.

• B side downstream transmitter activity level of a node.

(SCF bits + number of downstream transmitted data bits) ÷

1024.

The activity level for upstream data of TRX A is determined by

the following:

• Header bits for upstream. (SRF bits + total number of

received downstream data bits) ÷ 1024.

• The number of upstream data bits transmitted in a node =

number of upstream transmitted slots × (bits per slot +

parity bit) where the parity bit = 1. The number of

upstream transmitted slots is the sum of received upstream

slots and locally contributed slots.

• A side upstream transmitter activity level of a node. 

(SRF bits + number of transmitted upstream data bits) ÷

1024.

LVDS Transmitter and Receiver Idle Current

The idle current, ITRXVDD_IDLE, depends on ITXVDD and IRXVDD at

0% activity level and A2B bus idle time.

• B transceiver idle current. B Transceiver IBTRXVDD_IDLE

LVDS current results from B transceiver idle time.

•A transceiver idle current. A Transceiver IATRXVDD_IDLE

LVDS current results from A transceiver idle time.

• B transceiver idle time. B transceiver idle time is the time

when both the TX and RX of the B transceiver are idle.

The idle time of the B transceiver is derived by eliminating

the following activity levels from the B transceiver frame

cycle:

• B transceiver downstream activity level of the current

node.

• A transceiver upstream activity level of the next in line

node.

• A transceiver idle time is the time when both the TX and

RX of the A transceiver are idle.

The idle time of the A transceiver is derived by eliminating

the following activity from the A transceiver frame cycle:

• A transceiver upstream activity level of the current

node.

• B transceiver downstream activity level of previous

node.

The sum of the LVDS transceiver currents is

ITRXVDD = IBRXVDD + IBTXVDD + IARXVDD + IATXVDD + 

IBTRXVDD_IDLE + IATRXVDD_IDLE

VREG1 AND VREG2 OUTPUT CURRENTS

Voltage regulator output currents are governed by the following

equations:

IVOUT2 is the current from VVOUT2 which is the sum of the LVDS

transmitter and receiver supply currents, peripheral supply cur-

rents, and I/O current.

IVOUT2 = ITRXVDD + IIOVDD+ IVEXT2

IVOUT1 is the current from the VOUT1 pin which is the sum of PLL

supply current, IPLLVDD, digital logic supply current IDVDD,

peripheral supply current, IVEXT1, and I

2S/TDM/PDM I/O cur-

rent IIOVDD.

IVOUT1 = IPLLVDD + IVEXT1 + IDVDD + IIOVDD

IIOVDD in a subordinate node can be sourced by either IVOUT1 or

IVOUT2 but not both, depending on whether IIOVDD is supplied

from VVOUT1 or VVOUT2.

AD2426 Datasheet(PDF) 29 Page - Analog Devices

AD2426 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL