Rev. F

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Page 16 of 38

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November 2023

AD2426/AD2427/AD2428

POWER-UP SEQUENCING RESTRICTIONS

When externally supplied, VDVDD and VIOVDD must reach at least 90% of specification before VVIN begins ramping.

To avoid damage to input pins and to ensure correct sampling of the ADR1/ADR2 pins at startup, VIOVDD must be within specification

before input signals are driven by external devices.

Table 8. Power-Up Timing

Parameter

Min

Max

Unit

Timing Requirements

tVIN

When Externally Supplied, VDVDD and VIOVDD Must Reach 90% of Specification

Before VVIN Begins Ramping

>0

ms

tPORST

Minimum Time Required for VVIN to be Held Below VRST to Assert Power on Reset 25

ms

Figure 14. Power-Up Sequencing Timing with Externally Supplied VDVDD and VIOVDD

VDVDD

| VIOVDD

VVIN

tVIN

tPORST

VRST

MIN

VRSTN

MAX