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AD9171 Datasheet(PDF) 40 Page - Analog Devices

Part # AD9171
Description  Dual, 16-Bit, 6.2 GSPS RF DAC with Single Channelizer
PDF  134 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9171 Datasheet(HTML) 40 Page - Analog Devices

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Data Sheet
AD9171
DIGITAL DATAPATH
analog.com
Rev. C | 40 of 134
The full digital datapath of the AD9171 consists of channel data-
paths that are bypassable, as well as a main DAC datapath leading
up to the analog DAC core. There is a variety of different digital
feature blocks available within each of the channel and main DAC
datapaths.
TOTAL DATAPATH INTERPOLATION
The AD9171 contains two separate blocks of interpolation: one
located in each of the channelizer datapaths, and a second inter-
polation stage located in the main DAC datapath. The total interpo-
lation for the chip can be determined by multiplying the channel
interpolation factor by the main datapath interpolation factor. The
relationship between the DAC sample rate and input data rate is
shown in the following equation:
TotalInterpolation = (ChannelInterpolation × MainInterpolation)
fDATA = fDAC / (ChannelInterpolation × MainInterpolation)
Each of the various cascaded half-band filters has 80% signal
bandwidth capabilities. Therefore, if using interpolation (not bypass
or 1× total interpolation for both channel and main datapaths), the
available signal bandwidth (BW) with respect to the input data rate
is calculated as follows:
SignalBW = 0.8 × (fDATA/2)
where the total interpolation > 1.
SignalBW = (fDATA /2)
where the total interpolation = 1.
The interpolation values are programmed as shown in Table 29.
Table 29. Interpolation Factor Register Settings
Interpolation
Factor
Main Datapath, Register
0x111, Bits[7:4]
Channel Datapath, Register
0x111, Bits[3:0]
2×
Not applicable
0x2
3×
Not applicable
0x3
4×
Not applicable
0x4
6×
0x6
0x6
8×
0x8
Not applicable
Table 30. Interpolation Modes and Useable Bandwidth
Total Interpolation
Available Signal
Bandwidth
fDATA
12×, 16×, 18×, 24×, 32×,
36×, 48×, 64×
80% × fDATA /2
fDAC/total interpolation
Filter Performance
The interpolation filters interpolate between existing data in such
a way that they minimize changes in the incoming data while
suppressing the creation of interpolation images.
The usable bandwidth, as shown in Table 30 is defined as the
frequency band over which the filters have a pass-band ripple of
less than ±0.001 dB and an image rejection of greater than 85 dB.
The maximum pass-band amplitude of all filters is the same; they
are different in the illustration to improve understanding.
Figure 43. Band Responses of Total Interpolation Rates for 8×, 12×, 16×, 18×,
24×, 32×, 36×, 48×, and 64× at a 6 GHz DAC Rate, 16-Bit
NCO Only Mode
The AD9171 is capable of operating in a mode with only the NCO
enabled. In this mode, a single-tone sine wave is generated using
a programmable internal dc amplitude level that is injected into the
NCO block to modulate the data into a single tone. This internal dc
level is injected into either the channel or main datapaths through
various controls, as shown in Figure 44. Mode 3 can be used to
generate a single-channel NCO only mode of operation. It is not
necessary to bring up the JESD204B link in this mode. This mode
is a useful option to bring up a transmitter radio signal chain without
requiring a digital data source, because the device generates the
NCO data internally.
This mode can also be used in applications where a sine wave is
all that is required, such as in a local oscillator application. There
is an additional optional calibration NCO block that can be used as
part of the initial system calibration without needing to reprogram
the final main datapath NCO to the final system configuration. This
feature is discussed in more detail in the Calibration NCO section.
When the NCO test mode is enabled, the data source of the digital
datapath is the dc test data word, meaning that the JESD204B
link can be brought up and data can be transferred to the device
over the link, but the data is not presented to the DAC when in
this test mode. Connection to the SERDES data source is only
achieved by disabling this test mode. The SPI control bit for this
test mode can be set on the fly, but because disabling the mode
and switching to the SERDES datapath normally requires the lanes
and/or interpolation mode to also be set, on the fly setting or
resetting of the NCO only mode control bit is normally not practical.



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