AD9171 datasheet(49/134 Pages) AD

49 / 134 page

Data Sheet

AD9171

DIGITAL DATAPATH

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Rev. C | 49 of 134

Figure 56. Mode 3—DAC0 = I0 + I1, DAC1 = 0

Ramp Up/Down Gain

In each of the main datapaths, the ramp-up and ramp-down gain

block is immediately before the digital datapath enters the analog

DAC core for decoding. This block works in conjunction with the

power detection and protection (PDP) block to protect any down-

stream components from large power peaks or long, high average

power.

Various trigger signals can be configured in the PA protection

block to trigger a gain ramp-down to mute the data being trans-mit-

ted out of the DAC, as shown in Figure 49. The ramp-up and

ramp-down steps can be configured via the SPI in Register 0x580,

Bits[2:0]. The equation for the ramp-up and ramp-down occurs in

32 steps over 2(CODE + 8) DAC clock periods. This control can be

configured individually for each of the DAC ramp blocks via the

MAINDAC_PAGE control in Register 0x008.

After the data is ramped down from one of the triggers, it can

be ramped back up in two of the following ways after the error

condition is cleared. If the SPI protection control bit triggered the

interrupt for a ramp-down, the SPI is then also used to ramp the

data back up by toggling Register 0x582, Bit 7 from 0 to 1, and then

back to 0.

Additionally, an option exists to mute the digital data during a digital

clock rotation if the ROTATE_SOFT_OFF_EN control in Register

0x581, Bit 2 is set to 1. When this bit is set, the synchronization

logic rotation triggers the DAC ramp-down block, rotates the digital

clocks, and ramps back up. These actions only occur if Bit 1 of the

ROTATION_MODE control in Register 0x03B is set to 1 to enable a

datapath clock rotation when the synchronization logic rotates.

AD9171 Datasheet(PDF) 49 Page - Analog Devices