AD9171 datasheet(13/134 Pages) AD

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Data Sheet

AD9171

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. C | 13 of 134

Table 11. Pin Function Descriptions

Pin No.

Mnemonic

Description

C6, D3, D10, E3, E10

DVDD1.8

1.8 V Digital Supplies to the JESD204B Data Interface and the Other Input/Output Circuitry, Such

as the Serial Port Interface (SPI). Clean power supply rail sources are required on these pins.

Ground

A1, A6, A7, A12, B1, B6, B7, B12, C3, C4, C9,

C10, D5, D7, F1 to F3, F10 to F12, G1 to G12,

H11, J1, J3 to J5, J8 to J11, K2, K8, K9, K11, K12,

L2, L4, L5, L8, L9, L11, M1, M3, M6, M7, M10,

M12

GND

Device Common Ground.

RF Clock

J12

CLKIN+

Positive Device Clock Input. This pin is the clock input for the on-chip DAC clock multiplier,

REFCLK, when the DAC PLL is on. This pin is also the clock input for the DAC sample clock or

device clock (DACCLK) when the DAC PLL is off. AC couple this input. There is an internal 100 Ω

resistor between this pin and CLKIN−.

H12

CLKIN−

Negative Device Clock Input.

CLKOUT+

Positive Device Clock Output. This pin is the clock output of a divided down DACCLK and is

available with the DAC PLL on and off. The divide down ratios are by 1, 2, or 4.

CLKOUT−

Negative Device Clock Output.

System Reference

SYSREF+

Positive System Reference Input. It is recommended to ac couple this pin, but dc coupling is also

acceptable. See Table 6 for the dc common-mode voltage.

SYSREF−

Negative System Reference Input. It is recommended to ac couple this pin, but dc coupling is also

acceptable. See Table 6 for the dc common-mode voltage.

On-Chip DAC PLL Loop Filter

FILT_FINE

On-Chip DAC Clock Multiplier and PLL Fine Loop Filter Input.

FILT_COARSE

On-Chip DAC Clock Multiplier and PLL Coarse Loop Filter Input.

FILT_BYP

On-Chip DAC Clock Multiplier and LDO Bypass.

FILT_VCM

On-Chip DAC Clock Multiplier and VCO Common-Mode Input.

SERDES Data Bits

SERDIN7+

SERDES Data Bit 7, Positive.

SERDIN7−

SERDES Data Bit 7, Negative.

SERDIN6+

SERDES Data Bit 6, Positive.

SERDIN6−

SERDES Data Bit 6, Negative.

SERDIN5+

SERDES Data Bit 5, Positive.

SERDIN5−

SERDES Data Bit 5, Negative.

SERDIN4+

SERDES Data Bit 4, Positive.

SERDIN4−

SERDES Data Bit 4, Negative.

SERDIN3+

SERDES Data Bit 3, Positive.

SERDIN3−

SERDES Data Bit 3, Negative.

SERDIN2+

SERDES Data Bit 2, Positive.

SERDIN2−

SERDES Data Bit 2, Negative.

A10

SERDIN1+

SERDES Data Bit 1, Positive.

B10

SERDIN1−

SERDES Data Bit 1, Negative.

A11

SERDIN0+

SERDES Data Bit 0, Positive.

B11

SERDIN0−

SERDES Data Bit 0, Negative.

Sync Output

D12

SYNCOUT0+

Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or CMOS selectable.

D11

SYNCOUT0−

Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or CMOS selectable.

SYNCOUT1+

Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or CMOS selectable.

SYNCOUT1−

Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or CMOS selectable.

Serial Port Interface

AD9171 Datasheet(PDF) 13 Page - Analog Devices

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