KSI-W001-000

10

Timing Diagram(Continued)

SD60C31/P SD60C51/P

ALE

PSEN

PORT0

PORT2

Figure 3. External Data Memory Write Cycle

WR

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A15 FROM PCH

A0 - A7 FROM PCL

INSTR IN

DATA OUT

A0 - A7

FROM RI OR DPL

- 0.5

0.45V

-0.1

Figure 4. Ex ternal Clock Drive

Figure 5. AC T es ting Input/ Output

+0.9

-0.5

0.45V

NOTE :

'1' and 0.45V for a logic '0'. Timing measurements are

Figure 6. Float Waveform

NOTE :

For timing purposes, a port is no longer floating when a

100mV change from load v oltage occurs, and begings

lev el occurs.

20mA

TIMING

REFERENCE

POINTS

- 0.1V

+ 0.1V

+ 0.1V

- 0.1V

≥±