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LM2506 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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LM2506 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 19 page ![]() Pin Descriptions - RGB Mode Pin Name No. of Pins I/O, Type Description RGB Serializer RGB Deserializer MPL SERIAL BUS PINS MD[1:0] 2 IO, MPL MPL Data Line Driver MPL Data Receiver MC 1 IO, MPL MPL Clock Line Driver MPL Clock Receiver V SSA Ground MPL Ground - see Power/Ground Pins CONFIGURATION/PARALLEL BUS PINS RGB* 1 I, LVCMOS RGB Mode Input Tie Low M/S* 1 I, LVCMOS Tie High for Serializer (Master) Tie Low for Deserializer (Slave) TM 1 I, LVCMOS Test Mode control input Tie Low (normal mode) RM0 1 I, LVCMOS RGB Mode control input zero Tie Low RM1 1 I, LVCMOS RGB Mode control input one Tie Low CLOCK / POWER DOWN SIGNALS PCLK 1 IO, LVCMOS PCLK input PCLK output PD OUT* 1O, LVCMOS Power Down Output, L = device in Power Down H = Device active. NA PD* 1 I, LVCMOS Power Down input, L = Powered down (sleep mode) H = active mode PARALLEL INTERFACE SIGNALS D[17:0] 18 IO, LVCMOS RGB Data Bus inputs RGB Data Bus outputs VS 1 IO, LVCMOS Vertical Sync. Input Vertical Sync. Output HS 1 IO, LVCMOS Horizontal Sync. Input Horizontal Sync. Output DE 1 IO, LVCMOS Data Enable Input Data Enable Output PE 1 O, LVCMOS NA Parity Error Output POWER/GROUND PINS V DDA 1 Power Power Supply Pin for the SER PLL and MPL Interface. 1.74V to 2.0V V SSA 1 Ground Ground Pin for the MPL Interface, and analog circuitry. V DDcore 1 Power Power Supply Pin for the digital core. 1.74V to 2.0V V SScore 1 Ground Ground Pin for the digital core. V DDIO 2 Power Power Supply Pin for the parallel interface I/Os. 1.74V to 3.0V V SSIO 2 Ground Ground Pin for the parallel interface I/Os. V bulk 9 Connect to Ground - uArray Package DAP 1 Connect to Ground - LLP Package Note: I = Input, O = Output, IO = Input/Output. Do not float input pins. www.national.com 3 |
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