LM2506 datasheet(12/19 Pages) NSC

12 / 19 page

LM2506 Features and Operation

POWER SUPPLIES

The V

DDcore and VDDA (MPL and PLL) must be connected to

the same potential between 1.74V and 2.0V. V

DDIO powers

the logic interface and may be powered between 1.74 and

3.0V to be compatible with a wide range of host and target

devices. On this device, V

DDIO should be powered up

before V

DDcore/VDDA or at the same time as VDDcore/

DDAfor proper device configuration.

BYPASS RECOMMENDATIONS

Bypass capacitors should be placed near the power supply

pins of the device. Use high frequency ceramic (surface

mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF

Tantalum capacitor is recommended near the SER V

DDA pin

for PLL bypass. Connect bypass capacitors with wide traces

and use dual or larger via to reduce resistance and induc-

tance of the feeds. Utilizing a thin spacing between power

and ground planes will provide good high frequency bypass

above the frequency range where most typical surface

mount capacitors are less effective. To gain the maximum

benefit from this, low inductance feed points are important.

Also, adjacent signal layers can be filled to create additional

capacitance. Minimize loops in the ground returns also for

improved signal fidelity and lowest emissions.

UNUSED/OPEN PINS

Unused inputs must be tied to the proper input level — do not

float them. Unused outputs should be left open to minimize

power dissipation.

PHASE-LOCKED LOOP

When the LM2506 is configured as a RGB Serializer, a PLL

is enabled to generate the serial link clock. The Phase-

locked loop system generates the serial data clock at 6X of

the input clock. The MC rate must be between 12 and 80

MHz (PCLKs from 2 to 13.3 MHz).

MASTER(SER)/SLAVE(DES) SELECTION

The M/S* pin is used to configure the device as either a SER

or DES device. When the M/S* pin is a Logic High, the

Serializer (SER) configuration is selected. The Driver block

is enabled for the MC line, and the MD lines. When the M/S*

pin is a Logic Low, the Deserializer (DES) configuration is

selected. The Receiver block is enabled for the MC line, and

the MD lines.

POWER DOWN/OFF CONFIGURATION / OPTIONS AND

CLOCK STOP

Power Up Operation - Upon the application of power to the

LM2506, devices configured as a DES activate all outputs.

Outputs are held in deasserted states, with all zeros on the

data busses until valid data is received from the SER. If PD*

is asserted (Low) prior to the application of power, then the

part remains in its power down state.

On both the SER and the DES, the PD* pin resets the logic.

The PD* pins should be held low until the power supply

has ramped up and is stable and within specifications.

Power Down and the use of the PD* Input - When the PD*

signal is asserted low, the entire chip regardless of mode,

powers down. A Low on the PD* input pin will power down

the entire device and turn off the line current to MD0, MD1,

and MC. In this state the following outputs are driven to:

SER:

OUT = Low

DES:

DATAn = PCLK = Low,

VS=HS=DE=PE=Low

Multiple configurations for PowerDown are possible with the

chipset. These depend on the operating mode and configu-

ration chosen. Two possible applications are shown in Figure

14. RGB Modes are shown in (A) and (B). "A" provides PD*

input pins on both devices, this may be common or seperate.

In (B), the SER is controlled by the PCLK STOP feature and

a PDOUT* pin is provided to control the DES. When using

the SER PD

OUT* mode, the VDDIO rails of the devices should

be the same to meet the PD* input thresholds of the DES.

The LM2506 provides a PCLK STOP feature on the SER

device. Gating of the pixel clock signal can be used to

generate a control signal for the SER to Power down or start

up. When a loss of pixel clock is detected (PLL out of lock),

the SER PD

OUT* pin is driven Low and the SER powers

down. When a PCLK is reapplied, the SER powers up, and

the PLL locks to the incoming clock signal. After 4,096 cycles

(t0), the SER MPL outputs are enabled and the DES is

calibrated. Once this is complete (t1 + t2 + t3), data trans-

mission can occur. See Figures 3, 4. The stopping of the

pixel clock should be done cleanly. Floating of the PCLK

input pin is not recommended.

LM2506 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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