AM79C940 datasheet(58/144 Pages) AMD

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Am79C940

of data in a transmit frame is being written to the

XMTFIFO, by asserting the EOF signal.

Transmit Frame Control (XMTFC)

(REG ADDR 2)

The Transmit Frame Control register is latched inter-

nally on the last write to the Transmit FIFO for each in-

dividual packet, when EOF is asserted. This permits

automatic transmit padding and FCS generation on a

packet-by-packet basis.

Bit

Name

Description

Bit 7

DRTRY

Disable Retry. When DRTRY is

set, the MACE device will pro-

vide a single transmission at-

tempt for the packet, all further

retries will be suspended. In the

case of a collision during the at-

tempt, a Retry Error (RTRY) will

be reported in the Transmit Sta-

tus. With DRTRY cleared, the

MACE device will attempt up to

15 retries (16 attempts total) be-

fore indicating a Retry Error.

DRTRY is cleared by activation

of the RESET pin or SWRST bit.

DRTRY is sampled during the

transmit

process

when

collision occurs. DRTRY should

not be changed whilst data

remains in the Transmit FIFO

since this may cause an unpre-

dictable retry response to a colli-

sion. Once the Transmit FIFO is

empty, DRTRY can be repro-

grammed.

Bit 6-4

RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 3

DXMTFCS

Disable Transmit FCS. When

DXMTFCS = 0 the transmitter

will generate and append an

FCS to the transmitted frame.

When DXMTFCS = 1, no FCS

will be appended to the transmit-

ted frame, providing that APAD

XMT is also clear. If APAD XMT

is set, the calculated FCS will be

appended to the transmitted

message regardless of the state

of DXMTFCS. The value of

DXMTFCS for each frame is

programmed when EOF is as-

serted to transfer the last byte/

word for the transmit packet to

the FIFO. DXMTFCS is cleared

by activation of the RESET pin

or SWRST bit. DXMTFCS is

sampled only when EOF is

asserted during a Transmit FIFO

write.

Bit

Name

Description

Bit 2-1

RES

Reserved.

Read

zeroes.

Always write as zeroes.

Bit 0

APAD XMT Auto Pad Transmit. APAD XMT

enables the automatic padding

feature. Transmit frames will be

padded to extend them to 64

bytes including FCS. The FCS is

calculated for the entire frame

including pad, and appended af-

ter the pad field. APAD XMT will

override the programming of the

DXMTFCS bit. APAD XMT is set

by activation of the RESET pin

or SWRST bit. APAD XMT is

sampled only when EOF is as-

serted during a Transmit FIFO

write.

Transmit Frame Status (XMTFS)

(REG ADDR 3)

The Transmit Frame Status is valid when the XMTSV

bit is set. The register is read only, and is cleared when

XMTSV is set and a read operation is performed. The

XMTINT bit in the Interrupt Register will be set when

any bit is set in this register.

Note that if XMTSV is not set, the values in this register

can change at any time, including during a read opera-

tion. This register should be read after the Transmit

Retry Count (XMTRC). See the description of the

Transmit Retry Count (XMTRC) for additional details.

Bit

Name

Description

Bit 7

XMTSV

Transmit Status Valid. Transmit

Status Valid indicates that this

status is valid for the last frame

transmitted.

The

value

XMTSV will not change during a

read operation.

Bit 6

UFLO

Underflow. Indicates that the

Transmit FIFO emptied before

the end of frame was reached.

The transmitted frame is truncat-

ed at that point. If UFLO is set,

TDTREQ will be de-asserted,

and will not be re-asserted until

the XMTFS has been read.

Bit 5

LCOL

Late Collision. Indicates that a

collision occurred after the slot

time of the channel elapsed. If

LCOL is set, TDTREQ will be

de-asserted, and will not be

DRTRY

RES

DXMTFCS

RES

APAD XMT

XMTSV

UFLO

LCOL

ONE

DEFER

LCAR

RTRY

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