The data field is the last 8-bit long sequence sent, followed by a last acknowledgement.

Table 6. TSC1214 address format

b7

b6

b5

b4

b3

b2

b1

b0

1

1

1

0

0

0

0

R/W

Table 7. Register address format

b7

b6

b5

b4

b3

b2

b1

b0

RegADDR7

RegADDR6

RegADDR5

RegADDR4

RegADDR3

RegADDR2

RegADDR1

RegADDR0

Table 8. Device data format

b7

b6

b5

b4

b3

b2

b1

b0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Figure 8. Read operation

Start

Device addr

Reg address

8 bits

A Restart

Device addr

A

Reg data

8 bits

A Reg data

8 bits

A

Reg data

8 bits

A

Address

n+1

Start bit = SDA falling when SCL = 1

7 bits

7 bits

Stop

A

W

Stop bit = SDA rising when SCL = 1

Restart bit = start after a start

Master

Slave

Acknowledge = SDA forced low during a SCL clock

R

Address

n+2

Figure 9. Write operation

Start

Device addr

Reg address

8 bits

A Reg data

A Reg data

8 bits

A

Reg data

8 bits

A

Address

n+1

Start bit = SDA falling when SCL = 1

7 bits

8 bits

Stop

A

W

Stop bit = SDA rising when SCL = 1

Restart bit = start after a start

Address

n+2

TSC1214

Application information

DS14731 - Rev 1

page 8/18