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AD7768BSTZ Datasheet(PDF) 3 Page - Analog Devices |
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AD7768BSTZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 106 page  Data Sheet AD7768/AD7768-4 TABLE OF CONTENTS analog.com Rev. C | 3 of 106 Digital Filter RAM Built In Self Test (BIST) Register.......................................................... 99 Status Register.................................................99 Revision Identification Register...................... 100 GPIO Control Register................................... 100 GPIO Write Data Register.............................. 100 GPIO Read Data Register..............................101 Analog Input Precharge Buffer Enable Register Channel 0 and Channel 1 ............. 101 Analog Input Precharge Buffer Enable Register Channel 2 and Channel 3.............. 101 Positive Reference Precharge Buffer Enable Register........................................................ 102 Negative Reference Precharge Buffer Enable Register............................................102 Offset Registers..............................................102 Gain Registers................................................103 Sync Phase Offset Registers......................... 103 ADC Diagnostic Receive Select Register.......103 ADC Diagnostic Control Register................... 104 Modulator Delay Control Register.................. 104 Chopping Control Register............................. 105 Outline Dimensions........................................... 106 Ordering Guide...............................................106 Evaluation Boards.......................................... 106 REVISION HISTORY 8/2022—Rev. B to Rev. C Changes to Features Section.......................................................................................................................... 1 Changes to General Description Section.........................................................................................................4 Changes to Specifications Section.................................................................................................................. 5 Changes to Table 9........................................................................................................................................22 Changes to Table 10......................................................................................................................................26 Changes to Figure 28 Caption....................................................................................................................... 32 Change to AC Common-Mode Rejection Ratio (AC CMRR) Section............................................................ 40 Changes to Power Supplies Section..............................................................................................................46 Changes to Recommended Power Supply Configuration Section.................................................................46 Changes to Analog Supply Internal Connectivity Section..............................................................................47 Changes to Pin Control Section.....................................................................................................................47 Change to SPI Control Functionality Section.................................................................................................51 Changes to Reset over SPI Control Interface Section...................................................................................52 Changes to CRC Protection Section..............................................................................................................53 Changes to ADC Synchronization over SPI Section......................................................................................53 Changes to Clock Selection Section..............................................................................................................58 Change to Table 28 Title................................................................................................................................ 60 Change to Table 29 Title................................................................................................................................ 61 Changes to Modulator Saturation Point Section............................................................................................ 64 Changes to Gain Adjustment Section............................................................................................................ 64 Changes to Daisy-Chaining Section.............................................................................................................. 71 Changes to Table 43......................................................................................................................................81 Change to Interface Configuration Register Section......................................................................................83 Changes to Digital Filter RAM Built In Self Test (BIST) Register Section...................................................... 83 Changes to Status Register Section.............................................................................................................. 84 Changes to Offset Registers Section.............................................................................................................88 Changes to Table 63......................................................................................................................................92 Changes to Table 67......................................................................................................................................96 Changes to Interface Configuration Register Section....................................................................................98 Changes to Digital Filter RAM Built In Self Test (BIST) Register Section...................................................... 99 Changes to Status Register Section.............................................................................................................. 99 |
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