AD7768BSTZ datasheet(58/106 Pages) AD

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Data Sheet

AD7768/AD7768-4

CIRCUIT INFORMATION

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Rev. C | 58 of 106

VCM

The AD7768/AD7768-4 provide a buffered common-mode voltage

output on Pin 59. This output can bias up analog input signals. By

incorporating the VCM buffer into the ADC, the AD7768/AD7768-4

reduce component count and board space. In pin control mode, the

VCM potential is fixed to (AVDD1 − AVSS)/2, and is enabled by

default.

In SPI control mode, configure the VCM potential using the general

configuration register (Register 0x05). The output can be enabled

or disabled, and set to (AVDD1 − AVSS)/2, 1.65 V, 2.14 V, or 2.5 V,

with respect to AVSS.

The VCM voltage output is associated with the Channel 0 circuitry.

If Channel 0 is put into standby mode, the VCM voltage output is

also disabled for maximum power savings. Channel 0 must be ena-

bled while VCM is being used externally to the AD7768/AD7768-4.

REFERENCE INPUT

The AD7768/AD7768-4 have two differential reference input pairs.

On the AD7768 REF1+ and REF1− are the reference inputs for

Channel 0 to Channel 3, and REF2+ and REF2− are for Channel

4 to Channel 7. On the AD7768-4 REF1+ and REF1− are the

reference inputs for Channel 0 and Channel 1, and REF2+ and

REF2− are for Channel 2 and Channel 3. The absolute input

reference voltage range is 1 V to AVDD1 − AVSS.

Like the analog inputs, the reference inputs have a precharge

buffer option. Each ADC has an individual buffer for each REFx+

and REFx−. The precharge buffers help reduce the burden on the

external reference circuitry.

In pin control mode, the reference precharge buffers are off by

default. In SPI control mode, the user can enable or disable the ref-

erence precharge buffers. In the case of unipolar analog supplies,

in SPI control mode, the user can achieve the best performance

and power efficiency by enabling only the REFx+ buffers. The

reference input current scales linearly with the modulator clock rate.

For 32 MHz MCLK and MCLK/4 fast mode, the differential input

current is ~72 µA/V per channel unbuffered, and ~16 µA/V per

channel with the precharge buffers enabled.

With the precharge buffers off, REFx+ = 5 V, and REFx− = 0 V,

REFx± = 5 V × 72 µA/V = 360 µA

With the precharge buffers on, REFx+ = 5 V, and REFx− = 0 V,

REFx± = 5 V × 16 µA/V = 80 µA

For the best performance and headroom, it is recommended to use

a 4.096 V reference such as the ADR444 or the ADR4540.

For the best performance at high sampling rates, it is recommended

to use an external reference drive amplifier such as the ADA4841-1

or the AD8031. See Figure 88 for the configuration diagram of the

reference connection.

Figure 88. Typical Reference Input Configuration Diagram

CLOCK SELECTION

The AD7768/AD7768-4 have an internal oscillator that is used for

initial power-up of the device. After the AD7768/AD7768-4 have

completed their start-up routine, the devices normally transfer con-

trol of the internal clocking to the externally applied MCLK. The

AD7768/AD7768-4 count the falling edges of the external MCLK

over a given number of internal clock cycles to determine if the

clock is valid and at least a frequency of 1.15 MHz. If there is a

fault with the external MCLK, the transfer of control does not occur,

the AD7768/AD7768-4 output an error in the status header, and the

clock error bit is set in the device status register. No conversion

data is output and a reset is required to exit this error state.

Three clock source input options are available to the AD7768/

AD7768-4: external CMOS, crystal oscillator, or LVDS. The clock

is selected on power-up and is determined by the state of the

CLK_SEL pin.

If CLK_SEL = 0, the CMOS clock option is selected and the clock is

applied to Pin 32 (Pin 31 is tied to DGND).

If CLK_SEL = 1, the crystal or LVDS option is selected and the

crystal or LVDS is applied to Pin 31 and Pin 32. The LVDS option

is available only in SPI control mode. Channel 4 on the AD7768

must be enabled in the channel standby register to use the crystal

because this is linked to the crystal excitation circuitry. On the

AD7768-4, Channel 2 must be enabled in the channel standby

To enable the LVDS clock, there are two options. Set GPIO4

to an output, then writing to the LVDS bit field in the POWER_

CLOCK register enables the LVDS clock. Or, set GPIO4 to an

input. Then GPIO4 must be tied to Logic 0. An SPI write to Bit 3

of Register 0x04 enables the LVDS clock option and disables the

crystal excitation circuitry.

DIGITAL FILTERING

The AD7768/AD7768-4 offer two types of digital filters. In SPI

control mode, these filters can be chosen on a per channel basis.

In pin control mode, only one filter can be selected for all channels.

The digital filters available on the AD7768/AD7768-4 are as follows:

►

Sinc5 low latency filter, −3 dB at 0.204 × ODR

►

Wideband low ripple filter, −3 dB at 0.433 × ODR

Both filters can be operated in one of six different decimation rates,

allowing the user to choose the optimal input bandwidth and speed

of the conversion versus the desired power mode or resolution.

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