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AD7768BSTZ Datasheet(PDF) 27 Page - Analog Devices |
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AD7768BSTZ Datasheet(HTML) 27 Page - Analog Devices |
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27 / 106 page  Data Sheet AD7768/AD7768-4 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS analog.com Rev. C | 27 of 106 Table 10. AD7768-4 Pin Function Descriptions Pin No. Mnemonic Type1 Description In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-purpose input/output pins (GPIO4 to GPIO0). See Table 75 for more details. 16 ST0/CS DI Standby 0/Chip Select Input. In pin control mode, a Logic 1 on this pin places Channel 0 to Channel 3 into standby mode. In SPI control mode, this pin is the active low chip select input to the SPI control interface. The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768-4. The crystal excitation circuitry is associated with the Channel 2 circuitry. If Channel 2 is put into standby mode, the crystal circuitry is also disabled for maximum power savings. Channel 2 must be enabled while the external crystal is used on the AD7768-4. 17 SCLK DI Serial Clock Input. In SPI control mode, this pin is the serial clock input pin for the SPI control interface. In pin control mode, tie this pin to a Logic 0 or DGND. 18 DEC1/SDI DI Decimation Rate Control Input 1/Serial Data Input. In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table 17 in the Setting the Decimation Rate section. In SPI control mode, this pin is the serial data input pin used to write data to the AD7768-4 register bank. 19 DEC0/SDO DI/O Decimation Rate Control Input 0/Serial Data Output. In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table 17 in the Setting the Decimation Rate section. In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7768-4 registers. 20 DNC/DGND DO/DI Do Not Connect/Digital Ground. This is an unused pin. Leave this pin floating if FORMAT0 is tied to logic low. If FORMAT0 is tied to logic high, connect this pin to DGND through a pull-down resistor. 21 DIN DI Data Input Daisy Chain. This pin acts as a digital input from a separate AD7768-4 device if configured in a synchronized multidevice daisy chain. To use this pin in a daisy chain, hardwire the FORMAT0 pin to logic high. If FORMAT0 is tied to logic low, or the daisy-chaining input pin is not used, then tie this pin to DGND through a pull-down resistor. 22, 23 DNC DO Do Not Connect. Do not connect to this pin. 24 DOUT3 DO Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY. 25 DOUT2 DO Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY. 26 DOUT1 DO Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY. 27 DOUT0 DO Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY. 28 DCLK DO ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (DSP/FPGA). This pin is synchronous with DRDY and any conversion data output on DOUT0 to DOUT3 and is derived from the MCLK signal. This pin is unrelated to the control SPI interface. 29 DRDY DO Data Ready. DRDY is a periodic signal output framing the conversion results from the four ADCs. This pin is synchronous to DCLK and DOUT0 to DOUT3. 30 RESET DI Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to perform a hard reset using this pin or, alternatively, to perform a soft reset by issuing a reset over the SPI control interface. 31 XTAL1 DI Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND. In SPI control mode, when using a crystal source, the FILTER pin must be set to Logic 1 for correct operation. When used with an LVDS clock, it is recommended that this pin be connected to one trace of the LVDS signal pair. When used as an LVDS input, a rising edge on this pin is detected as a rising MCLK edge by the AD7768-4. 32 XTAL2/MCLK DI Input 2 for CMOS/Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this configuration. External crystal: XTAL2 is connected to the external crystal. In SPI control mode, when using a crystal source, the FILTER pin must be set to Logic 1 for correct operation. LVDS: when used with an LVDS clock, connect this pin to the second trace of the LVDS signal pair. |
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