AD7768BSTZ datasheet(49/106 Pages) AD

49 / 106 page

Data Sheet

AD7768/AD7768-4

APPLICATIONS INFORMATION

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Rev. C | 49 of 106

Figure 77. AD7768-4 Pin Configurable Functions

Table 20. MODEx Selection Details: Pin Control Mode

Mode Hex.

MODE3

MODE2

MODE1

MODE0

Power Mode

DCLK Frequency

Data Conversion

0x0

Low power

MCLK/1

Standard

0x1

Low power

MCLK/2

Standard

0x2

Low power

MCLK/4

Standard

0x3

Low power

MCLK/8

Standard

0x4

Median

MCLK/1

Standard

0x5

Median

MCLK/2

Standard

0x6

Median

MCLK/4

Standard

0x7

Median

MCLK/8

Standard

0x8

Fast

MCLK/1

Standard

0x9

Fast

MCLK/2

Standard

0xA

Fast

MCLK/4

Standard

0xB

Fast

MCLK/8

Standard

0xC

Low power

MCLK/1

One-shot

0xD

Median

MCLK/1

One-shot

0xE

Fast

MCLK/2

One-shot

0xF

Fast

MCLK/1

One-shot

Configuration Example

In the example shown in Table 23, the lowest current consumption

is used, and the AD7768/AD7768-4 are connected to an FPGA.

The FORMATx pins are set such that all eight data outputs, DOUT0

to DOUT7, connect to the FPGA. For the lowest power, the lowest

DCLK frequency is used. The input bandwidth is set through the

combination of selecting decimation by 64 and selecting the wide-

band filter.

ODR = fMOD ÷ Decimation Ratio

where:

fMOD is MCLK/32 for low power mode (see Table 19).

MCLK = 32.768 MHz.

Decimation Ratio = 64.

Therefore, for this example, where MCLK = 32.768 MHz,

ODR = (32.768 MHz/32) ÷ 64 = 16 kHz

Minimizing the DCLK frequency means selecting DCLK = MCLK/8,

which results in a 4 MHz DCLK signal. The period of DCLK in this

case is 1/4 MHz = 250 ns. The data conversion on each DOUTx

pin is 32 bits long. The conversion data takes 32 × 250 ns = 8

µs to be output. All 32 bits must be output within the ODR period

of 1/16 kHz, which is approximately 64 µs. In this case, the 8 µs

required to read out the conversion data is well within the 64 µs

between conversion outputs. Therefore, this combination, which is

summarized in Table 23, is viable for use.

Channel Standby

Table 21 and Table 23 show how the user can put channels into

standby mode. Set either ST0 or ST1 to Logic 1 to place banks

of four channels into standby mode. When in standby mode, the

channels are disabled but still hold their position in the output data

stream. The 8-bit header and 24-bit conversion result are set to all

zeros when the ADC channels are set to standby.

AD7768BSTZ Datasheet(PDF) 49 Page - Analog Devices

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