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M68HC08 Datasheet(PDF) 107 Page - Freescale Semiconductor, Inc |
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M68HC08 Datasheet(HTML) 107 Page - Freescale Semiconductor, Inc |
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107 / 288 page  System Integration Module (SIM) MC68HC908BD48 — Rev. 2.1 Data Sheet Freescale Semiconductor System Integration Module (SIM) 107 A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-16 shows stop mode entry timing. Figure 7-16. Stop Mode Entry Timing Figure 7-17. Stop Mode Recovery from Interrupt or Break STOP ADDR + 1 SAME SAME IAB IDB PREVIOUS DATA NEXT OPCODE SAME STOP ADDR SAME R/W CPUSTOP NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. OSCXCLK INT/BREAK IAB STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 STOP +1 STOP RECOVERY PERIOD |
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