M68HC08 datasheet(109/288 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

System Integration Module (SIM)

109

SBSW can be read within the break interrupt routine. The user can

modify the return address on the stack by subtracting one from it. The

following code is an example.

7.8.2 SIM Reset Status Register (SRSR)

This register contains six flags that show the source of the last reset.

Clear the SIM reset status register by reading it. A power-on reset sets

the POR bit and clears all other bits in the register.

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

;

This code works if the H register has been pushed onto the stack in the break

service routine software. This code should be executed at the end of the break

service routine software.

HIBYTE

EQU

LOBYTE

EQU

;

If not SBSW, do RTI

BRCLR

SBSW,SBSR, RETURN

;

See if wait mode or stop mode was exited by

break.

TST

LOBYTE,SP

;If RETURNLO is not zero,

BNE

DOLO

;then just decrement low byte.

DEC

HIBYTE,SP

;Else deal with high byte, too.

DOLO

DEC

LOBYTE,SP

;Point to WAIT/STOP opcode.

RETURN

PULH

RTI

;Restore H register.

Address:

$FE01

Bit 7

654321

Bit 0

Read:

POR

COP

ILOP

ILAD

Write:

POR:

10000000

= Unimplemented

Figure 7-19. SIM Reset Status Register (SRSR)

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