M68HC08 datasheet(106/288 Pages) FREESCALE

106 / 288 page

System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

106

System Integration Module (SIM)

Freescale Semiconductor

Figure 7-14. Wait Recovery from Interrupt or Break

Figure 7-15. Wait Recovery from Internal Reset

7.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are

disabled. An interrupt request from a module can cause an exit from stop

mode. Stacking for interrupts begins after the selected stop recovery

time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in

stop mode, stopping the CPU and peripherals. Stop recovery time is

selectable using the SSREC bit in configuration register 1 (CONFIG1). If

SSREC is set, stop recovery is reduced from the normal delay of 4096

OSCXCLK cycles down to 32. This is ideal for applications using canned

oscillators that do not require long start-up times from stop mode.

NOTE:

External crystal applications should use the full stop recovery time by

clearing the SSREC bit.

$6E0C

$6E0B

$00FF

$00FE

$00FD

$00FC

$A6

$01

$0B

$6E

$A6

IAB

IDB

EXITSTOPWAIT

NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt

IAB

IDB

RST

$A6

$6E0B

RST VCT H RST VCT L

$A6

OSCXCLK

Cycles

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