M68HC08 datasheet(110/288 Pages) FREESCALE

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System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

110

System Integration Module (SIM)

Freescale Semiconductor

PIN — External Reset Bit

1 = Last reset caused by external reset pin (RST)

0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter

0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

7.8.3 SIM Break Flag Control Register (SBFCR)

The SIM break flag control register contains a bit that enables software

to clear status bits while the MCU is in a break state.

BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing

status registers while the MCU is in a break state. To clear status bits

during the break state, the BCFE bit must be set.

1 = Status bits clearable during break

0 = Status bits not clearable during break

Address:

$FE03

Bit 7

654321

Bit 0

Read:

BCFE

RRRRRRR

Write:

Reset:

R= Reserved

Figure 7-20. SIM Break Flag Control Register (SBFCR)

M68HC08 Datasheet(PDF) 110 Page - Freescale Semiconductor, Inc