M68HC08 datasheet(132/288 Pages) FREESCALE

132 / 288 page

Timer Interface Module (TIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

132

Timer Interface Module (TIM)

Freescale Semiconductor

Figure 10-2. PWM Period and Pulse Width

The value in the TIM counter modulo registers and the selected

prescaler output determines the frequency of the PWM output. The

frequency of an 8-bit PWM signal is variable in 256 increments. Writing

$00FF (255) to the TIM counter modulo registers produces a PWM

period of 256 times the internal bus clock period if the prescaler select

value is 000 (see 10.10.1 TIM Status and Control Register (TSC)).

The value in the TIM channel registers determines the pulse width of the

PWM output. The pulse width of an 8-bit PWM signal is variable in 256

increments. Writing $0080 (128) to the TIM channel registers produces

a duty cycle of 128/256 or 50%.

10.5.4.1 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PWM pulses as

described in 10.5.4 Pulse Width Modulation (PWM). The pulses are

unbuffered because changing the pulse width requires writing the new

pulse width value over the old value currently in the TIM channel

registers.

An unsynchronized write to the TIM channel registers to change a pulse

width value could cause incorrect operation for up to two PWM periods.

For example, writing a new value before the counter reaches the old

value but after the counter reaches the new value prevents any compare

during that PWM period. Also, using a TIM overflow interrupt routine to

write a new, smaller pulse width value may cause the compare to be

missed. The TIM may pass the new value before it is written.

TCHx

PERIOD

PULSE

WIDTH

OVERFLOW

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

M68HC08 Datasheet(PDF) 132 Page - Freescale Semiconductor, Inc