M68HC08 datasheet(136/288 Pages) FREESCALE

136 / 288 page

Timer Interface Module (TIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

136

Timer Interface Module (TIM)

Freescale Semiconductor

10.8 TIM During Break Interrupts

A break interrupt stops the TIM counter.

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the break flag control register (BFCR) enables software to clear status

bits during the break state. (See 7.8.3 SIM Break Flag Control Register

(SBFCR).)

To allow software to clear status bits during a break interrupt, write a

logic one to the BCFE bit. If a status bit is cleared during the break state,

it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic zero to the

BCFE bit. With BCFE at logic zero (its default state), software can read

and write I/O registers during the break state without affecting status

bits. Some status bits have a two-step read/write clearing procedure. If

software does the first step on such a bit before the break, the bit cannot

change during the break state as long as BCFE is at logic zero. After the

break, doing the second step clears the status bit.

10.9 I/O Signals

Port E shares one of its pins with the TIM. The TIM channel I/O pin is

PTE0/SOG/TCH0.

TCH0 pin is programmable independently as an input capture pin or an

output compare pin. It also can be configured as a buffered output

compare or buffered PWM pin.

M68HC08 Datasheet(PDF) 136 Page - Freescale Semiconductor, Inc