M68HC08 datasheet(138/288 Pages) FREESCALE

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Timer Interface Module (TIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

138

Timer Interface Module (TIM)

Freescale Semiconductor

clearing sequence is complete, then writing logic zero to TOF has no

effect. Therefore, a TOF interrupt request cannot be lost due to

inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic

one to TOF has no effect.

1 = TIM counter has reached modulo value

0 = TIM counter has not reached modulo value

TOIE — TIM Overflow Interrupt Enable Bit

This read/write bit enables TIM overflow interrupts when the TOF bit

becomes set. Reset clears the TOIE bit.

1 = TIM overflow interrupts enabled

0 = TIM overflow interrupts disabled

TSTOP — TIM Stop Bit

This read/write bit stops the TIM counter. Counting resumes when

TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM

counter until software clears the TSTOP bit.

1 = TIM counter stopped

0 = TIM counter active

NOTE:

Do not set the TSTOP bit before entering wait mode if the TIM is required

to exit wait mode.

TRST — TIM Reset Bit

Setting this write-only bit resets the TIM counter and the TIM

prescaler. Setting TRST has no effect on any other registers.

Counting resumes from $0000. TRST is cleared automatically after

the TIM counter is reset and always reads as logic zero. Reset clears

the TRST bit.

1 = Prescaler and TIM counter cleared

0 = No effect

NOTE:

Setting the TSTOP and TRST bits simultaneously stops the TIM counter

at a value of $0000.

PS[2:0] — Prescaler Select Bits

These read/write bits select either the TCLK pin or one of the seven

prescaler outputs as the input to the TIM counter as Table 10-3

shows. Reset clears the PS[2:0] bits.

M68HC08 Datasheet(PDF) 138 Page - Freescale Semiconductor, Inc