M68HC08 datasheet(137/288 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Timer Interface Module (TIM)

137

10.10 I/O Registers

The following I/O registers control and monitor operation of the TIM:

•

TIM status and control register (TSC)

•

TIM counter registers (TCNTH:TCNTL)

•

TIM counter modulo registers (TMODH:TMODL)

•

TIM channel status and control registers (TSC0 and TSC1)

•

TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)

10.10.1 TIM Status and Control Register (TSC)

The TIM status and control register does the following:

•

Enables TIM overflow interrupts

•

Flags TIM overflows

•

Stops the TIM counter

•

Resets the TIM counter

•

Prescales the TIM counter clock

TOF — TIM Overflow Flag Bit

This read/write flag is set when the TIM counter reaches the modulo

value programmed in the TIM counter modulo registers. Clear TOF by

reading the TIM status and control register when TOF is set and then

writing a logic zero to TOF. If another TIM overflow occurs before the

Address:

$000A

Bit 7

654321

Bit 0

Read:

TOF

TOIE

TSTOP

PS2

PS1

PS0

Write:

TRST

Reset:

00100000

= Unimplemented

Figure 10-3. TIM Status and Control Register (TSC)

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