M68HC08 datasheet(133/288 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Timer Interface Module (TIM)

133

Use the following methods to synchronize unbuffered changes in the

PWM pulse width on channel x:

•

When changing to a shorter pulse width, enable channel x output

compare interrupts and write the new value in the output compare

interrupt routine. The output compare interrupt occurs at the end

of the current pulse. The interrupt routine has until the end of the

PWM period to write the new value.

•

When changing to a longer pulse width, enable TIM overflow

interrupts and write the new value in the TIM overflow interrupt

routine. The TIM overflow interrupt occurs at the end of the current

PWM period. Writing a larger value in an output compare interrupt

routine (at the end of the current pulse) could cause two output

compares to occur in the same PWM period.

NOTE:

In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on output compare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self-

correct in the event of software error or noise. Toggling on output

compare also can cause incorrect PWM signal generation when

changing the PWM pulse width to a new, much larger value.

10.5.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the TCH0 pin. The TIM channel registers of the linked

pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)

links channel 0 and channel 1. The TIM channel 0 registers initially

control the pulse width on the TCH0 pin. Writing to the TIM channel 1

registers enables the TIM channel 1 registers to synchronously control

the pulse width at the beginning of the next PWM period. At each

subsequent overflow, the TIM channel registers (0 or 1) that control the

pulse width are the ones written to last. TSC0 controls and monitors the

buffered PWM function, and TIM channel 1 status and control register

(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,

is available as a general-purpose I/O pin.

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