M68HC08 datasheet(144/288 Pages) FREESCALE

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Timer Interface Module (TIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

144

Timer Interface Module (TIM)

Freescale Semiconductor

NOTE:

Before enabling a TIM channel register for input capture operation, make

sure that the TCHx pin is stable for at least two bus clocks.

TOVx — Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit

controls the behavior of the channel x output when the TIM counter

overflows. When channel x is an input capture channel, TOVx has no

effect. Reset clears the TOVx bit.

1 = Channel x pin toggles on TIM counter overflow.

0 = Channel x pin does not toggle on TIM counter overflow.

NOTE:

When TOVx is set, a TIM counter overflow takes precedence over a

channel x output compare if both occur at the same time.

CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic one, setting the CHxMAX bit forces the

duty cycle of buffered and unbuffered PWM signals to 100%. As

Figure 10-7 shows, the CHxMAX bit takes effect in the cycle after it

is set or cleared. The output stays at the 100% duty cycle level until

the cycle after CHxMAX is cleared.

Table 10-4. Mode, Edge, and Level Selection

MSxB

MSxA

ELSxB

ELSxA

Mode

Configuration

Output

Preset

Pin under Port Control;

Initial Output Level High

Pin under Port Control;

Initial Output Level Low

Input

Capture

Capture on Rising Edge Only

Capture on Falling Edge Only

Capture on Rising or Falling Edge

Output

Compare

or PWM

Toggle Output on Compare

Clear Output on Compare

Set Output on Compare

Buffered

Output

Compare or

Buffered

PWM

Toggle Output on Compare

Clear Output on Compare

Set Output on Compare

M68HC08 Datasheet(PDF) 144 Page - Freescale Semiconductor, Inc

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